Datasheet KSZ9897S (Microchip) - 17

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KSZ9897S TABLE 3-3: CONFIGURATION STRAP DESCRIPTIONS (CONTINUED) Configuration Description Strap Pin LED4_0, LED2_0 When LED2_1 = 1 at strap-in (Normal Link-up): [LED4_0, LED2_0]: Auto-Negotiation Enable (All PHYs) / NAND Tree Test Mode
00: Reserved 01: Auto-negotiation disabled, forced as 100 Mbps and half duplex. Auto-MDI-X is on. 10: NAND Tree test mode 11: Auto-negotiation enabled (Default)
When LED2_1 = 0 at strap-in (Fast Link-up; All PHYs Full-Duplex; Auto-negotiation and Auto-MDI-X are off): LED2_0: 1000BASE-T Master/Slave Mode, 100BASE-T MDI/MDI-X Mode (All PHYs)
0: 1000BASE-T: Slave Mode 100BASE-T: MDI-X 1: 1000BASE-T: Master Mode (Default) 100BASE-T: MDI (Default)
LED4_0: PHY Speed Select (All PHYs)
0: 1000BASE-T 1: 100BASE-TX (Default)
LED4_1, LED3_1 [LED4_1, LED3_1]: Management Interface Mode
00: MIIM (MDIO) 01: I2C 1x: SPI (Default)
LED5_1 Switch Enable at Startup
0: Start Switch is disabled. The switch will not forward packets until the Start Switch bit is set in the Switch Operation Register. 1: Start Switch is enabled. The switch will forward packets immediately after reset. (Default)
RXD6_3, RXD6_2 [RXD6_3, RXD6_2]: Port 6 Mode
00: RGMII (Default) 01: RMII 10: Reserved 11: MII
RXD6_1 Port 6 MII/RMII Mode
0: MII: PHY Mode (Default) RMII: Clock Mode. RMII 50MHz reference clock is output on
REFCLKO6
. (Default) RGMII: No effect 1: MII: MAC Mode RMII: Normal Mode. RMII 50MHz reference clock is input on
REFCLKI6
. RGMII: No effect
RXD6_0 Port 6 Speed Select
0: 1000Mbps Mode (Default) 1: 100Mbps Mode
Note:
If Port 6 is configured for MII or RMII, set the speed to 100Mbps.
IBA In-Band Management
0: Disable In-Band Management (Default) 1: Enable In-Band Management
CLKO_25_125 SGMII Mode C
0: Invalid 1: Normal SGMII operation. This pin must be strapped high for proper operation. (Default)
INTRP_N SGMII Mode J
0: Invalid 1: Normal SGMII operation. This pin must be strapped high for proper operation. (Default)  2017-2019 Microchip Technology Inc. DS00002394C-page 17 Document Outline 1.0 Preface 1.1 Glossary of Terms TABLE 1-1: General Terms 1.2 Buffer Types TABLE 1-2: Buffer Types 1.3 Register Nomenclature TABLE 1-3: Register Nomenclature 1.4 References 2.0 Introduction 2.1 General Description FIGURE 2-1: Internal Block Diagram 3.0 Pin Descriptions and Configuration 3.1 Pin Assignments FIGURE 3-1: Pin Assignments (Top View) TABLE 3-1: Pin Assignments 3.2 Pin Descriptions TABLE 3-2: Pin Descriptions 3.2.1 Configuration Straps TABLE 3-3: Configuration Strap Descriptions 4.0 Functional Description 4.1 Physical Layer Transceiver (PHY) 4.1.1 1000BASE-T Transceiver 4.1.2 100BASE-TX Transceiver 4.1.3 10BASE-Te Transceiver 4.1.4 Auto MDI/MDI-X TABLE 4-1: MDI/MDI-X Pin Definitions 4.1.5 Pair-Swap, Alignment, and Polarity Check 4.1.6 Wave Shaping, Slew-Rate Control, and Partial Response 4.1.7 Auto-Negotiation FIGURE 4-1: Auto-Negotiation and Parallel Operation 4.1.8 Fast Link-Up 4.1.9 LinkMD® Cable Diagnostics 4.1.10 Remote PHY Loopback FIGURE 4-2: Remote PHY Loopback 4.2 LEDs 4.2.1 Single-LED Mode TABLE 4-2: Single-LED Mode Pin Definition 4.2.2 Tri-Color Dual-LED Mode TABLE 4-3: Tri-Color Dual-LED Mode Pin Definition 4.3 Media Access Controller (MAC) 4.3.1 MAC Operation 4.3.2 Inter-Packet Gap (IPG) 4.3.3 Back-Off Algorithm 4.3.4 Late Collision 4.3.5 Legal Packet Size 4.3.6 Flow Control 4.3.7 Half-Duplex Back Pressure 4.3.8 Flow Control and Back Pressure Registers TABLE 4-4: Flow Control and back Pressure Registers 4.3.9 Broadcast Storm Protection 4.3.10 Self-Address Filtering 4.4 Switch 4.4.1 Switching Engine 4.4.2 Address Lookup TABLE 4-5: Address Lookup Table Hashing Options TABLE 4-6: Reserved Multicast Address Table FIGURE 4-3: Packet Forwarding Process Flowchart TABLE 4-7: Lookup Engine Registers 4.4.3 IEEE 802.1Q VLAN TABLE 4-8: VLAN Forwarding TABLE 4-9: Hashed(DA) + FID Lookup in VLAN Mode TABLE 4-10: Hashed(SA) + FID Lookup in VLAN Mode TABLE 4-11: VLAN Registers 4.4.4 Quality-of-Service (QoS) Priority Support FIGURE 4-4: 802.p Priority Field Format 4.4.5 Traffic Conditioning & Policing 4.4.6 Spanning Tree Support TABLE 4-12: Spanning Tree States 4.4.7 Rapid Spanning Tree Support 4.4.8 Multiple Spanning Tree Support 4.4.9 Tail Tagging Mode FIGURE 4-5: Tail Tag Frame Format TABLE 4-13: Receive Tail Tag Format (from Switch to Host) TABLE 4-14: Transmit Tail Tag Format (from Host to Switch) 4.4.10 IGMP Support 4.4.11 IPv6 MLD Snooping 4.4.12 Port Mirroring 4.4.13 Scheduling and Rate Limiting 4.4.14 Ingress MAC Address Filtering Function 4.4.15 802.1X Access Control 4.4.16 Access Control List (ACL) Filtering TABLE 4-15: ACL Processing Entry Parameters FIGURE 4-6: ACL Structure and Example Rule Values TABLE 4-16: Matching Rule Options TABLE 4-17: ACL Matching Rule Parameters for MD = 01 TABLE 4-18: ACL Matching Rule Parameters for MD = 10 TABLE 4-19: ACL Matching Rule Parameters for MD = 11 TABLE 4-20: ACL Action Rule Parameters for Non-count Modes (MD ≠ 01 or ENB ≠ 00) TABLE 4-21: ACL Action Rule Parameters for count Mode (MD = 01 or ENB = 00) FIGURE 4-7: ACL Table Format TABLE 4-22: ACL Registers 4.5 NAND Tree Support TABLE 4-23: NAND Tree Test Pin Order 4.6 Clocking 4.6.1 Primary Clock 4.6.2 Port 6 RGMII/MII/RMII Clocks 4.6.3 Port 7 SGMII Clock 4.6.4 Serial Management Interface Clock 4.6.5 CLKO_25_125 4.7 Power FIGURE 4-8: Power Connection Diagram 4.8 Power Management TABLE 4-24: MDI/MDI-X Pin Definitions 4.8.1 Normal Operation Mode 4.8.2 Energy-Detect Mode 4.8.3 Global Soft Power-Down Mode 4.8.4 Port-Based Power Down 4.8.5 Wake on LAN (WoL) 4.9 Management Interface 4.9.1 SPI Slave Bus TABLE 4-25: Register Access using the SPI Interface FIGURE 4-9: SPI Register Read Operation FIGURE 4-10: SPI Register Write Operation 4.9.2 I2C Bus FIGURE 4-11: Single Byte Register Write FIGURE 4-12: Single Byte Register Read FIGURE 4-13: Burst Register Write FIGURE 4-14: Burst Register Read 4.9.3 MII Management (MIIM) Interface TABLE 4-26: MII Management Interface Frame Format TABLE 4-27: Standard MIIM Registers 4.10 In-Band Management FIGURE 4-15: In-Band Management Frame Format 4.11 MAC Interface (Ports 6 and 7) 4.11.1 Media Independent Interface (MII) (Port 6) TABLE 4-28: MII (PHY Mode) Connection to External MAC TABLE 4-29: MII (MAC Mode) Connection to External PHY 4.11.2 Reduced Media Independent Interface (RMII) (Port 6) TABLE 4-30: RMII Signal Descriptions TABLE 4-31: RMII Connection to External MAC TABLE 4-32: RMII Connection to External PHY 4.11.3 Reduced Gigabit Media Independent Interface (RGMII) (Port 6) TABLE 4-33: RGMII Signal Descriptions 4.11.4 Serial Gigabit Media Independent Interface (SGMII) (Port 7) 5.0 Device Registers FIGURE 5-1: Register Address Mapping FIGURE 5-2: Byte Ordering TABLE 5-1: Global Register Address Map TABLE 5-2: Port N (1-7) Register Address Map 5.1 Global Registers 5.1.1 Global Operation Control Registers (0x0000 - 0x00FF) 5.1.2 Global I/O Control Registers (0x0100 - 0x01FF) 5.1.3 Global PHY Control and Status Registers (0x0200 - 0x02FF) 5.1.4 Global Switch Control Registers (0x0300 - 0x03FF) 5.1.5 Global Switch Look Up Engine (LUE) Control Registers (0x0400 - 0x04FF) 5.2 Port Registers 5.2.1 Port N: Port Operation Control Registers (0xN000 - 0xN0FF) 5.2.2 Port N: Port Ethernet PHY Registers (0xN100 - 0xN1FF) 5.2.3 Port N: Port SGMII Control Registers (0xN200 - 0xN2FF) 5.2.4 Port N: Port RGMII/MII/RMII Control Registers (0xN300 - 0xN3FF) 5.2.5 Port N: Port Switch MAC Control Registers (0xN400 - 0xN4FF) TABLE 5-3: Data Rate Selection Table for Ingress and Egress Rate Limiting 5.2.6 Port N: Port Switch MIB Counters Registers (0xN500 - 0xN5FF) 5.2.7 Port N: Port Switch ACL Control Registers (0xN600 - 0xN6FF) 5.2.8 Port N: Port Switch Ingress Control Registers (0xN800 - 0xN8FF) 5.2.9 Port N: Port Switch Egress Control Registers (0xN900 - 0xN9FF) 5.2.10 Port N: Port Switch Queue Management Control Registers (0xNA00 - 0xNAFF) 5.2.11 Port N: Port Switch Address Lookup Control Registers (0xNB00 - 0xNBFF) 5.3 Tables and MIB Counters (Access) 5.3.1 Address Lookup (ALU) Table FIGURE 5-3: Address Lookup Table Configuration 5.3.2 Static Address Table 5.3.3 Reserved Multicast Address Table 5.3.4 VLAN Table FIGURE 5-4: VLAN Table Structure TABLE 5-4: VLAN Table Data Fields 5.3.5 Access Control List (ACL) Table TABLE 5-5: ACL Field Register Mapping 5.3.6 Management Information Base (MIB) Counters TABLE 5-6: MIB Counters 5.4 MDIO Manageable Device (MMD) Registers (Indirect) TABLE 5-7: MMD Register Map 5.4.1 MMD LED Mode Register 5.4.2 MMD EEE Advertisement Register 5.5 SGMII Registers (Indirect) TABLE 5-8: SGMII Register Map (Indirect) 5.5.1 SGMII Control Register 5.5.2 SGMII Status Register 5.5.3 SGMII PHY ID 1 Register 5.5.4 SGMII PHY ID 2 Register 5.5.5 SGMII Auto-Negotiation Advertisement Register 5.5.6 SGMII Auto-Negotiation Link Partner Base Ability Register 5.5.7 SGMII Auto-Negotiation Expansion Register 5.5.8 SGMII Digital Control Register 5.5.9 SGMII Auto-Negotiation Control Register 5.5.10 SGMII Auto-Negotiation Status Register 6.0 Operational Characteristics 6.1 Absolute Maximum Ratings* 6.2 Operating Conditions** 6.3 Electrical Characteristics TABLE 6-1: Electrical Characteristics 6.4 Timing Specifications 6.4.1 RGMII Timing FIGURE 6-1: RGMII Timing TABLE 6-2: RGMII Timing Values 6.4.2 MII Timing FIGURE 6-2: MII Transmit Timing in MAC Mode TABLE 6-3: MII Transmit Timing in MAC Mode Values FIGURE 6-3: MII Receive Timing in MAC Mode TABLE 6-4: MII Receive Timing in MAC Mode Values FIGURE 6-4: MII Receive Timing in PHY Mode TABLE 6-5: MII Receive Timing in PHY Mode Values FIGURE 6-5: MII Transmit Timing in PHY Mode TABLE 6-6: MII Transmit Timing in PHY Mode Values 6.4.3 RMII Timing FIGURE 6-6: RMII Transmit Timing FIGURE 6-7: RMII Receive Timing TABLE 6-7: RMII Timing Values 6.4.4 MIIM Timing FIGURE 6-8: MIIM Timing TABLE 6-8: MIIM Timing Values 6.4.5 SPI Timing FIGURE 6-9: SPI Data Input Timing FIGURE 6-10: SPI Data Output Timing TABLE 6-9: SPI Timing Values 6.4.6 Auto-Negotiation Timing FIGURE 6-11: Auto-Negotiation Timing TABLE 6-10: Auto-Negotiation Timing Values 6.4.7 Power-up and Reset Timing FIGURE 6-12: Power-up and Reset Timing TABLE 6-11: Power-up and Reset Timing Values 6.5 Clock Specifications FIGURE 6-13: Input Reference Clock Connection Options TABLE 6-12: Reference Crystal Characteristics 7.0 Design Guidelines 7.1 Reset Circuit Guidelines FIGURE 7-1: Simple Reset Circuit FIGURE 7-2: Reset Circuit for CPU Reset Interface 7.2 Magnetics Connection and Selection Guidelines FIGURE 7-3: Typical Magnetic Interface Circuit TABLE 7-1: Magnetics Selection Criteria TABLE 7-2: Compatible Single-Port 10/100/1000 Magnetics 8.0 Package Information 8.1 Package Marking Information 8.2 Package Drawings FIGURE 8-1: Package (Drawing) FIGURE 8-2: Package (Dimensions) FIGURE 8-3: Package (Land Pattern) Appendix A: Data Sheet Revision History The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service