Datasheet ADSP-BF531, ADSP-BF532, ADSP-BF533 (Analog Devices) - 2
| 制造商 | Analog Devices |
| 描述 | Blackfin Embedded Processor |
| 页数 / 页 | 64 / 2 — ADSP-BF531/. ADSP-BF532. /ADSP-BF533. TABLE OF CONTENTS. REVISION … |
| 修订版 | I |
| 文件格式/大小 | PDF / 2.5 Mb |
| 文件语言 | 英语 |
ADSP-BF531/. ADSP-BF532. /ADSP-BF533. TABLE OF CONTENTS. REVISION HISTORY. 8/13— Rev. H to Rev. I
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ADSP-BF531/ ADSP-BF532 /ADSP-BF533 TABLE OF CONTENTS
Features ... 1 Development Tools .. 15 Memory .. 1 Additional Information .. 16 Peripherals ... 1 Related Signal Chains ... 16 General Description ... 3 Pin Descriptions .. 17 Portable Low Power Architecture ... 3 Specifications .. 20 System Integration .. 3 Operating Conditions ... 20 Processor Peripherals ... 3 Electrical Characteristics ... 22 Blackfin Processor Core .. 4 Absolute Maximum Ratings ... 25 Memory Architecture .. 4 ESD Sensitivity ... 25 DMA Controllers .. 8 Package Information .. 26 Real-Time Clock ... 8 Timing Specifications ... 27 Watchdog Timer .. 9 Output Drive Currents ... 43 Timers ... 9 Test Conditions .. 45 Serial Ports (SPORTs) .. 9 Thermal Characteristics .. 49 Serial Peripheral Interface (SPI) Port ... 10 160-Ball CSP_BGA Ball Assignment ... 50 UART Port .. 10 169-Ball PBGA Ball Assignment ... 53 General-Purpose I/O Port F ... 10 176-Lead LQFP Pinout .. 56 Parallel Peripheral Interface ... 11 Outline Dimensions .. 58 Dynamic Power Management .. 11 Surface-Mount Design .. 61 Voltage Regulation .. 13 Automotive Products .. 62 Clock Signals ... 13 Ordering Guide ... 63 Booting Modes ... 14 Instruction Set Description ... 15
REVISION HISTORY 8/13— Rev. H to Rev. I
Updated Development Tools .. 15 Corrected Conditions value of the VIL specification in Operating Conditions ... 20 Added notes to Table 30 in Serial Ports—Enable and Three-State .. 36 Added Timer Clock Timing .. 41 Revised Timer Cycle Timing ... 41 Updated Ordering Guide ... 63 Rev. I | Page 2 of 64 | August 2013 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Portable Low Power Architecture System Integration Processor Peripherals Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Real-Time Clock Watchdog Timer Timers Serial Ports (SPORTs) Serial Peripheral Interface (SPI) Port UART Port General-Purpose I/O Port F Parallel Peripheral Interface General-Purpose Mode Descriptions Input Mode Frame Capture Mode Output Mode ITU-R 656 Mode Descriptions Active Video Only Mode Vertical Blanking Interval Mode Entire Field Mode Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings Voltage Regulation Voltage Regulator Layout Guidelines Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings ESD Sensitivity Package Information Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing SDRAM Interface Timing External Port Bus Request and Grant Cycle Timing Parallel Peripheral Interface Timing Serial Port Timing Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing General-Purpose I/O Port F Pin Cycle Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing Timer Clock Timing Timer Cycle Timing JTAG Test and Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Thermal Characteristics 160-Ball CSP_BGA Ball Assignment 169-Ball PBGA Ball Assignment 176-Lead LQFP Pinout Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide
ADSP-BF531/ ADSP-BF532 /ADSP-BF533 TABLE OF CONTENTS
Features ... 1 Development Tools .. 15 Memory .. 1 Additional Information .. 16 Peripherals ... 1 Related Signal Chains ... 16 General Description ... 3 Pin Descriptions .. 17 Portable Low Power Architecture ... 3 Specifications .. 20 System Integration .. 3 Operating Conditions ... 20 Processor Peripherals ... 3 Electrical Characteristics ... 22 Blackfin Processor Core .. 4 Absolute Maximum Ratings ... 25 Memory Architecture .. 4 ESD Sensitivity ... 25 DMA Controllers .. 8 Package Information .. 26 Real-Time Clock ... 8 Timing Specifications ... 27 Watchdog Timer .. 9 Output Drive Currents ... 43 Timers ... 9 Test Conditions .. 45 Serial Ports (SPORTs) .. 9 Thermal Characteristics .. 49 Serial Peripheral Interface (SPI) Port ... 10 160-Ball CSP_BGA Ball Assignment ... 50 UART Port .. 10 169-Ball PBGA Ball Assignment ... 53 General-Purpose I/O Port F ... 10 176-Lead LQFP Pinout .. 56 Parallel Peripheral Interface ... 11 Outline Dimensions .. 58 Dynamic Power Management .. 11 Surface-Mount Design .. 61 Voltage Regulation .. 13 Automotive Products .. 62 Clock Signals ... 13 Ordering Guide ... 63 Booting Modes ... 14 Instruction Set Description ... 15
REVISION HISTORY 8/13— Rev. H to Rev. I
Updated Development Tools .. 15 Corrected Conditions value of the VIL specification in Operating Conditions ... 20 Added notes to Table 30 in Serial Ports—Enable and Three-State .. 36 Added Timer Clock Timing .. 41 Revised Timer Cycle Timing ... 41 Updated Ordering Guide ... 63 Rev. I | Page 2 of 64 | August 2013 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Portable Low Power Architecture System Integration Processor Peripherals Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Real-Time Clock Watchdog Timer Timers Serial Ports (SPORTs) Serial Peripheral Interface (SPI) Port UART Port General-Purpose I/O Port F Parallel Peripheral Interface General-Purpose Mode Descriptions Input Mode Frame Capture Mode Output Mode ITU-R 656 Mode Descriptions Active Video Only Mode Vertical Blanking Interval Mode Entire Field Mode Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings Voltage Regulation Voltage Regulator Layout Guidelines Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings ESD Sensitivity Package Information Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing SDRAM Interface Timing External Port Bus Request and Grant Cycle Timing Parallel Peripheral Interface Timing Serial Port Timing Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing General-Purpose I/O Port F Pin Cycle Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing Timer Clock Timing Timer Cycle Timing JTAG Test and Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Thermal Characteristics 160-Ball CSP_BGA Ball Assignment 169-Ball PBGA Ball Assignment 176-Lead LQFP Pinout Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide