Datasheet ADL5569 (Analog Devices) - 16

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ADL5569 Data Sheet INPUT AND OUTPUT INTERFACING
where: The ADL5569 can be configured as a differential input to RG is the series resistance internal to the amplifier. differential output driver, as shown in Figure 40. The 50 Ω RF is feedback resistance internal to the amplifier. resistors, R1 and R2, combined with the input balun, provide a Thus, RIN = 91.7 Ω. 50 Ω input match for the 100 Ω input impedance. The input The next step is to calculate the termination of Resistor R2 (see and output 0.1 µF capacitors isolate the VVCC/VVCC2 bias from Figure 42). Because source impedance (RS) must be equal to the the source and balanced load. The load is 100 Ω to provide the parallel equivalent resistance of R2 and RIN, expected ac performance (see the Specifications section). R2 × R
V
IN
S
= S R R2 + RIN
0.1µF 1:1 BALUN 0.1µF
Thus,
+ 50Ω R2 ½ ½ RL
R2 = R
50Ω
IN × RS/(RIN − RS) (3)
ADL5569 0.1µF ½ R 0.1µF
When R
L
S = 50 Ω and RIN = 91.7 Ω, R2 = 109 Ω.
AC –
The last step is to calculate the gain path rebalancing resistor,
R1 50Ω
R1 (see Figure 42), by using the following formula: 105 15671- R × R2 Figure 40. Differential Input to Differential Output Configuration S R1 = (4) + S R R2 The differential gain of the ADL5569 is dependent on the source impedance and load, as shown in Figure 41. Determine the Thus, R1 = 34.0 Ω. differential gain (AV) by
RF
A
500Ω
V = 500/50 (1)
RG R 0.1µF 0.1µF F 50Ω 500Ω + ½ 0.1µF R R S R2 ½ L RG ADL5569 0.1µF 0.1µF ½ 50Ω ½ RG R 0.1µF AC L – R 50Ω S + ½ R1 RF AC R R G ADL5569 L 50Ω 0.1µF 500Ω
107
– ½
15671-
R S 0.1µF RF 500Ω
Figure 42. Single-Ended Input to Differential Output Configuration 106 See the AN-0990 Application Note, Terminating a Differential 15671- Amplifier in Single-Ended Input Applications, for more information Figure 41. Differential Input Loading Circuit on terminating single-ended inputs. The single-ended gain
Single-Ended Input to Differential Output
configuration of the ADL5569 is dependent on the source The ADL5569 can also be configured in a single-ended input to impedance and load, as shown in Figure 43. differential output configuration, as shown in Figure 42. In
RF 500Ω
this configuration, the gain of the device is reduced due to the application of the signal to only one side of the amplifier. The input
RG 0.1µF 0.1µF
and output 0.1 µF capacitors isolate the V
50Ω
VCC/VVCC2 bias from the
½ +
source and the balanced load.
R R2 R S ½ L 109Ω R ADL5569 G 0.1µF 0.1µF ½
The single-ended circuit configuration can be accomplished in
50Ω R AC L –
three steps (see Figure 42), assuming a 50 Ω RS source. First,
R1
calculate the input resistance (R
34.2Ω
IN) of the amplifier using the
RF
following formula:
500Ω
108 15671- G R R = Figure 43. Single-Ended Input Loading Circuit IN (2)   1– F R    2 (  × +  G R F R )  Rev. A | Page 16 of 23 Document Outline Features Applications Functional Block Diagram General Description Revision History Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Applications Information Basic Connections Input and Output Interfacing Single-Ended Input to Differential Output Gain Adjustment and Interfacing Effect of Load Capacitance GSPS ADC Interfacing Soldering Information and Recommended Land Pattern Evaluation Board Outline Dimensions Ordering Guide