Datasheet ADL5569 (Analog Devices) - 3
| 制造商 | Analog Devices |
| 描述 | 6.5 GHz, Ultrahigh Dynamic Range, Differential Amplifier |
| 页数 / 页 | 23 / 3 — Data Sheet. ADL5569. SPECIFICATIONS. Table 1. Parameter. Test … |
| 修订版 | C |
| 文件格式/大小 | PDF / 750 Kb |
| 文件语言 | 英语 |
Data Sheet. ADL5569. SPECIFICATIONS. Table 1. Parameter. Test Conditions/Comments. Min. Typ. Max. Unit
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Data Sheet ADL5569 SPECIFICATIONS
Supply voltage (VS) = 5 V, maximum gain, output common-mode voltage (VCOM) = VS/2, source impedance (RS) = 100 Ω differential, load impedance (RL) = 100 Ω differential, output voltage (VOUT) = 2 V p-p composite, frequency = 500 MHz, TA = 25°C, parameters specified for differential input and differential output, and signal spacing = 2 MHz for two tone measurements, unless otherwise noted.
Table 1. Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE −3 dB Bandwidth1 VOUT ≤ 0.5 V p-p 6.5 GHz Bandwidth, 1.0 dB Flatness VOUT ≤ 1.0 V p-p 4.8 GHz Voltage Gain (AV) Differential Input RL = open 20 dB RL = 100 Ω differential 6 19 dB Single-Ended Input RL = 100 Ω differential 6 17 dB Gain Accuracy ±0.15 dB Gain Supply Sensitivity VS ± 5% 8.6 mdB/V Gain Temperature Sensitivity TA = −40°C to +85°C 4 mdB/°C Slew Rate Rising, VOUT = 2 V p-p step 24 V/ns Falling, VOUT = 2 V p-p step 24 V/ns Settling Time 2 V step to 1% 500 ps Overdrive Recovery Time Differential input voltage step from 2 V to 6 ns 0 V for VOUT ≤ ±20 mV Reverse Isolation (SDD12) PDB and PDB2 are high −34 dB When Amplifier Disabled PDB and PDB2 are low −17.5 dB INPUT AND OUTPUT CHARACTERISTICS Input Common-Mode Range 1.3 3.5 V Input Resistance Differential 100 Ω Single-Ended 91.7 Ω Common-Mode Rejection Ratio (CMRR) 47 dB Output Common-Mode Range VCOM and VCOM2 2.0 3.0 V VCOM and VCOM2 Input Impedance 2.5 kΩ Output, Common Mode Referenced to VCOM (VS/2) Offset −30 ±10 +30 mV Drift TA = −40°C to +85°C 0.15 mV/°C Output, Differential Offset Voltage −10 ±1.5 +10 mV Drift TA = −40°C to +85°C ±6 µV/°C Output Resistance (Differential) 14.0 Ω Maximum Output Voltage Swing 1 dB compression point 6.5 V p-p POWER INTERFACE Supply Voltage 4.75 5 5.25 V Digital Input Voltage PDB, PDB2 Logic High (VIH) 2.1 3.45 V Logic Low (VIL) 0 1.0 V PDB Input Current PDB = 3 V −7 µA PDB = 0 V −70 µA Supply Current (ISUPPLY) Each amplifier Quiescent, Each Amplifier PDB is high 86 mA Disabled (Powered Down), Each Amplifier PDB is low 8 mA Rev. A | Page 3 of 23 Document Outline Features Applications Functional Block Diagram General Description Revision History Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Applications Information Basic Connections Input and Output Interfacing Single-Ended Input to Differential Output Gain Adjustment and Interfacing Effect of Load Capacitance GSPS ADC Interfacing Soldering Information and Recommended Land Pattern Evaluation Board Outline Dimensions Ordering Guide
Data Sheet ADL5569 SPECIFICATIONS
Supply voltage (VS) = 5 V, maximum gain, output common-mode voltage (VCOM) = VS/2, source impedance (RS) = 100 Ω differential, load impedance (RL) = 100 Ω differential, output voltage (VOUT) = 2 V p-p composite, frequency = 500 MHz, TA = 25°C, parameters specified for differential input and differential output, and signal spacing = 2 MHz for two tone measurements, unless otherwise noted.
Table 1. Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE −3 dB Bandwidth1 VOUT ≤ 0.5 V p-p 6.5 GHz Bandwidth, 1.0 dB Flatness VOUT ≤ 1.0 V p-p 4.8 GHz Voltage Gain (AV) Differential Input RL = open 20 dB RL = 100 Ω differential 6 19 dB Single-Ended Input RL = 100 Ω differential 6 17 dB Gain Accuracy ±0.15 dB Gain Supply Sensitivity VS ± 5% 8.6 mdB/V Gain Temperature Sensitivity TA = −40°C to +85°C 4 mdB/°C Slew Rate Rising, VOUT = 2 V p-p step 24 V/ns Falling, VOUT = 2 V p-p step 24 V/ns Settling Time 2 V step to 1% 500 ps Overdrive Recovery Time Differential input voltage step from 2 V to 6 ns 0 V for VOUT ≤ ±20 mV Reverse Isolation (SDD12) PDB and PDB2 are high −34 dB When Amplifier Disabled PDB and PDB2 are low −17.5 dB INPUT AND OUTPUT CHARACTERISTICS Input Common-Mode Range 1.3 3.5 V Input Resistance Differential 100 Ω Single-Ended 91.7 Ω Common-Mode Rejection Ratio (CMRR) 47 dB Output Common-Mode Range VCOM and VCOM2 2.0 3.0 V VCOM and VCOM2 Input Impedance 2.5 kΩ Output, Common Mode Referenced to VCOM (VS/2) Offset −30 ±10 +30 mV Drift TA = −40°C to +85°C 0.15 mV/°C Output, Differential Offset Voltage −10 ±1.5 +10 mV Drift TA = −40°C to +85°C ±6 µV/°C Output Resistance (Differential) 14.0 Ω Maximum Output Voltage Swing 1 dB compression point 6.5 V p-p POWER INTERFACE Supply Voltage 4.75 5 5.25 V Digital Input Voltage PDB, PDB2 Logic High (VIH) 2.1 3.45 V Logic Low (VIL) 0 1.0 V PDB Input Current PDB = 3 V −7 µA PDB = 0 V −70 µA Supply Current (ISUPPLY) Each amplifier Quiescent, Each Amplifier PDB is high 86 mA Disabled (Powered Down), Each Amplifier PDB is low 8 mA Rev. A | Page 3 of 23 Document Outline Features Applications Functional Block Diagram General Description Revision History Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Applications Information Basic Connections Input and Output Interfacing Single-Ended Input to Differential Output Gain Adjustment and Interfacing Effect of Load Capacitance GSPS ADC Interfacing Soldering Information and Recommended Land Pattern Evaluation Board Outline Dimensions Ordering Guide