Datasheet ISL70444SEH (Intersil) - 5

制造商Intersil
描述19MHz Radiation Hardened 40V Quad Rail-to-Rail Input - Output, Low-Power Operational Amplifiers
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修订版2017-12-21
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link. to. page. 5. link. to. page. 5. link. to. page. 5. link. to. page. 9. link. to. page. 9. ISL70444SEH. Absolute. Maximum. Ratings. Thermal. Information. Maximum. Supply

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link to page 5 link to page 5 link to page 5 link to page 9 link to page 9 ISL70444SEH Absolute Maximum Ratings Thermal Information Maximum Supply Voltage . 42V Thermal Resistance (Typical) JA (°C/W) JC (°C/W) Maximum Supply Voltage (Note 7). 42V 14 Ld Flatpack Package (Notes 5, 6). 35 9 Maximum Differential Input Current . 20mA Storage Temperature Range. .-65°C to +150°C Maximum Differential Input Voltage . 42V or V- - 0.5V to V+ + 0.5V Min/Max Input Voltage . 42V or V- - 0.5V to V+ + 0.5V Recommended Operating Conditions Max/Min Input Current for Input Voltage >V+ or <V- . ±20mA ESD Tolerance Ambient Operating Temperature Range . .-55°C to +125°C Human Body Model (Tested per MIL-PRF-883 3015.7). 2kV Maximum Operating Junction Temperature . .+150°C Machine Model (Tested per JESD22-A115-A) . 200V Single Supply Voltage. 3V ±10% to 36V ±10% Charged Device Model (Tested per CDM-22CI0ID). 750V Split Rail Supply Voltage . ±1.5V ±10% to ±18V ±10% CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 5. JA is measured in free air with the component mounted on a high-effective thermal conductivity test board with “direct attach” features. See TB379. 6. For JC, the “case temp” location is the center of the package underside. 7. Tested in a heavy ion environment at LET = 86.4MeV•cm2/mg at +125°C (TC) for SEB. Refer to Single Event Effects Test Report for more information. Electrical Specifications VS = ±18V VCM = VO = 0V, RL = Open, TA = +25°C, unless otherwise noted. Boldface limits apply across the operating temperature range, -55°C to +125°C. MIN MAX PARAMETER SYMBOL TEST CONDITIONS (Note 8) TYP (Note 8) UNIT Offset Voltage VOS VCM = 0V 20 400 µV VCM = V+ to V- 80 500 µV Offset Voltage Temperature Coefficient TCVOS VCM = V+ - 2V to V- + 2V 0.5 µV/°C Input Offset Channel-to-Channel Match VOS VCM = V+ 77 800 µV VCM = V- 117 800 µV Input Bias Current IB VCM = 0V 189 370 nA VCM = V+ 200 370 nA VCM = V- 262 650 nA VCM = V+ - 0.5V 200 370 nA VCM = V- + 0.5V 257 650 nA Input Offset Current IOS VCM = V+ to V- -30 0 30 nA -50 0 50 nA Common-Mode Input Voltage Range VCMIR V- V+ V Common-Mode Rejection Ratio CMRR VCM = V- to V+ 112 dB VCM = V- to V+ 70 dB VCM = V+ - 0.5V to V- + 0.5V 111 dB VCM = V+ - 0.5V to V- + 0.5V 80 dB Power Supply Rejection Ratio PSRR V- = -18V; V+ = 0.5V to 18V 128 dB V+ = 18V; V- = -0.5V to -18V 83 dB Open-Loop Gain AVOL RL = 10kΩ to ground 125 dB 96 dB Output Voltage High (VOUT to V+) VOH RL = No load 78 160 mV RL = 10kΩ 118 175 mV Output Voltage Low (VOUT to V-) VOL RL = No load 73 160 mV RL = 10kΩ 110 175 mV Output Short-Circuit Current ISRC Sourcing; VIN = 0V, VOUT = -18V 10 mA FN8411 Rev.4.00 Page 5 of 25 Jul 6, 2017 Document Outline Related Literature Features Applications Table of Contents Pin Configuration Pin Descriptions Ordering Information Absolute Maximum Ratings Thermal Information Recommended Operating Conditions Electrical Specifications VS = ±18V Electrical Specifications VS = ±2.5V Electrical Specifications VS = ±1.5V Electrical Specifications VS = ±18V - Post Radiation Electrical Specifications VS = ±2.5V - Post Radiation Electrical Specifications VS = ±1.5V - Post Radiation Typical Performance Curves Post High Dose Rate Radiation Characteristics Post Low Dose Rate Radiation Characteristics Applications Information Functional Description Operating Voltage Range Input Performance Input ESD Diode Protection Output Short-Circuit Current Limiting Output Phase Reversal Power Dissipation Unused Channel Configuration Die Characteristics Die Dimensions Interface Materials Glassivation Top Metallization Backside Finish Process Assembly Related Information Substrate Potential Additional Information Worst Case Current Density Transistor Count Weight of Packaged Device Lid Characteristics Metallization Mask Layout Revision History About Intersil Package Outline Drawing