Datasheet LTC1923 (Analog Devices) - 8

LTC1923
U U U PI FU CTIO S (GN Package/UH Package) PLLLPF (Pin 1/Pin 30):
This pin serves as the lowpass
SS (Pin 8/Pin 6):
The TEC current can be soft-started by filter for the phase-locked loop when the part is being adding a capacitor from this pin to ground. This capacitor synchronized. The average voltage on this pin equally will be charged by a 1.5µA current source. This pin connects alters both the oscillator charge and discharge currents, to one of the inverting inputs of the current limit compara- thereby changing the frequency of operation. Bringing the tor and allows the TEC current to be linearly ramped up from voltage on this pin above VDD – 0.4V signifies that the part zero. The voltage on this pin must be greater than 1.5V to will be used as the synchronization master. This allows allow the open/shorted thermistor window comparitor to multiple devices on the same board to be operated at the signal a fault. same frequency. The SDSYNC pin will be pulled low during
I
each C
LIM (Pin 9/Pin 7):
A voltage divider from VREF to this pin T charging cycle to facilitate synchronization. sets the current limit threshold for the TEC. If the voltage
RSLEW (Pin 2/Pin 31):
Placing a resistor from this pin to on this pin is set higher than 1V, then ILIMIT = 150mV/RS AGND sets the voltage slew rate of the output driver pins. as that is the internal current limit comparator level. If the The minimum resistor value is 10k and the maximum voltage on this pin is set less than 1V, the current limit value is 300k. Slew rate limiting can be disabled by tying value where the comparator trips is: this pin to VDD, allowing the outputs to transition at their I maximum rate. LIMIT = [0.15 • RILIM1 • VREF]/[(RILIM1 + RILIM2) • RS]
V SDSYNC (Pin 3/Pin 32):
This pin can be used to disable the
SET (Pin 10/Pin 8):
This is the input for the setpoint reference of the temperature sense element divider net- IC, synchronize the internal oscillator or be the master to work or bridge. This pin must be connected to the bias synchronize other devices. Grounding this pin will disable source for the thermistor divider network. all internal circuitry and cause NDRVA and NDRVB to be forced low and PDRVA and PDRVB to be forced to V
FAULT (Pin 11/Pin 9):
Open-drain output that indicates by DD. EAOUT will be forced low. FAULT will also be asserted low pulling low when the voltage on VTHRM is outside the indicating a fault condition. The pin can be pulled low for specified window, the part is in shutdown, undervoltage up to 20µs without triggering the shutdown circuitry. The lockout (UVLO), or the reference is not good. When the part can either be slaved to an external clock or can be used voltage on VTHRM is outside the specified window, it as the master (see Applications Information for a more signifies that the thermistor impedance is out of its accept- detailed explanantion). able range. This signal can be used to flag a microcontroller to shut the system down or used to disconnect power from
CNTRL (Pin 4/Pin 1):
Noninverting Input to the Error the bridge. See Applications Information for using this Amplifier. signal for redundant protection.
EAOUT (Pin 5/Pin 2):
Output of the Error Amplifier. The
V
loop compensation network is connected between this pin
THRM (Pin 12/Pin 10):
Voltage Across the Thermistor. If the voltage on this pin is outside the range between 410mV and FB. The voltage on this pin is the input to the PWM below V comparator and commands anywhere between 0% and SET and 0.2 • VSET, the FAULT pin will be asserted (and latched) low indicating that the thermistor tempera- 100% duty cycle to control the temperature of the tem- ture has moved outside the acceptable range. perature sense element.
H/C (Pin 13/Pin 11):
This open-drain output provides the
FB (Pin 6/Pin 3):
The Inverting Input to the Error Amplifier. direction information of the TEC current flow. If TEC+ is This input is connected to EAOUT through a compensating greater than TEC –, which typically corresponds to the feedback network. system cooling, this output will be a logic low. If the
AGND (Pin 7/Pin 4):
Signal Ground. All voltages are opposite is the case, this pin will pull to a logic high. measured with respect to AGND. Bypass VDD and VREF with low ESR capacitors to the ground plane near this pin. 1923f 8