Datasheet AD5686, AD5684 (Analog Devices) - 2
| 制造商 | Analog Devices |
| 描述 | Quad, 16-/12-Bit nanoDAC+ with SPI Interface |
| 页数 / 页 | 27 / 2 — AD5686/AD5684. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY … |
| 修订版 | C |
| 文件格式/大小 | PDF / 757 Kb |
| 文件语言 | 英语 |
AD5686/AD5684. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY 6/2017—Rev. B to Rev. C. 3/2015—Rev. A to Rev. B
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AD5686/AD5684 Data Sheet TABLE OF CONTENTS
Features .. 1 Serial Interface .. 19 Applications ... 1 Standalone Operation .. 20 Functional Block Diagram .. 1 Write and Update Commands .. 20 General Description ... 1 Daisy-Chain Operation ... 20 Product Highlights ... 1 Readback Operation .. 21 Revision History ... 2 Power-Down Operation .. 21 Specifications ... 3 Load DAC (Hardware LDAC Pin) ... 22 AC Characteristics .. 5 LDAC Mask Register ... 22 Timing Characteristics .. 6 Hardware Reset (RESET) .. 23 Daisy-Chain and Readback Timing Characteristics.. 7 Reset Select Pin (RSTSEL) .. 23 Absolute Maximum Ratings .. 9 Applications Information .. 24 ESD Caution .. 9 Microprocessor Interfacing ... 24 Pin Configurations and Function Descriptions ... 10 AD5686/AD5684 to ADSP-BF531 Interface .. 24 Typical Performance Characteristics ... 11 AD5686/AD5684 to SPORT Interface .. 24 Terminology .. 16 Layout Guidelines... 24 Theory of Operation .. 18 Galvanical y Isolated Interface ... 25 Digital-to-Analog Converter .. 18 Outline Dimensions ... 26 Transfer Function ... 18 Ordering Guide .. 27 DAC Architecture ... 18
REVISION HISTORY 6/2017—Rev. B to Rev. C 3/2015—Rev. A to Rev. B
Changes to Features Section 1 .. 1 Changes to Table 4 and Figure 2 .. 6 Changes to Table 2 .. 3 Inserted Note 2 to Ordering Guide .. 27 Changes to Table 3 .. 5 Changes to Table 4 .. 6
6/2013—Rev. 0 to Rev. A
Changes to Table 5 and Figure 4 ... 7 Changes to Pin GAIN and Pin RSTSEL Descriptions; Table 7 . 10 Changes to Figure 5 .. 8 Changes to Table 6 .. 9
7/2012—Revision 0: Initial Version
Change to VLOGIC Pin Description and RESET Pin Description, Table 7 .. 9 Changes to Figure 12 and Figure 13 ... 11 Changes to Figure 14 to Figure 19 .. 12 Changes to Figure 20, Figure 22, and Figure 25 ... 13 Changes to Figure 32 .. 15 Changes to Table 8 .. 19 Changes to Readback Operation Section .. 21 Changes to Hardware Reset (RESET) Section .. 23 Changes to Ordering Guide .. 27 Rev. C | Page 2 of 27 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS AC CHARACTERISTICS TIMING CHARACTERISTICS DAISY-CHAIN AND READBACK TIMING CHARACTERISTICS Circuit and Timing Diagrams ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION DIGITAL-TO-ANALOG CONVERTER TRANSFER FUNCTION DAC ARCHITECTURE Output Amplifiers SERIAL INTERFACE Input Shift Register STANDALONE OPERATION WRITE AND UPDATE COMMANDS Write to Input Register n (Dependent on LDACB) Update DAC Register n with Contents of Input Register n Write to and Update DAC Channel n (Independent of LDACB) DAISY-CHAIN OPERATION READBACK OPERATION POWER-DOWN OPERATION LOAD DAC (HARDWARE LDACB PIN) Instantaneous DAC Updating (LDACB Held Low) Deferred DAC Updating (LDACB Is Pulsed Low) LDACB MASK REGISTER HARDWARE RESET (RESETB) RESET SELECT PIN (RSTSEL) APPLICATIONS INFORMATION MICROPROCESSOR INTERFACING AD5686/AD5684 TO ADSP-BF531 INTERFACE AD5686/AD5684 TO SPORT INTERFACE LAYOUT GUIDELINES GALVANICALLY ISOLATED INTERFACE OUTLINE DIMENSIONS ORDERING GUIDE
AD5686/AD5684 Data Sheet TABLE OF CONTENTS
Features .. 1 Serial Interface .. 19 Applications ... 1 Standalone Operation .. 20 Functional Block Diagram .. 1 Write and Update Commands .. 20 General Description ... 1 Daisy-Chain Operation ... 20 Product Highlights ... 1 Readback Operation .. 21 Revision History ... 2 Power-Down Operation .. 21 Specifications ... 3 Load DAC (Hardware LDAC Pin) ... 22 AC Characteristics .. 5 LDAC Mask Register ... 22 Timing Characteristics .. 6 Hardware Reset (RESET) .. 23 Daisy-Chain and Readback Timing Characteristics.. 7 Reset Select Pin (RSTSEL) .. 23 Absolute Maximum Ratings .. 9 Applications Information .. 24 ESD Caution .. 9 Microprocessor Interfacing ... 24 Pin Configurations and Function Descriptions ... 10 AD5686/AD5684 to ADSP-BF531 Interface .. 24 Typical Performance Characteristics ... 11 AD5686/AD5684 to SPORT Interface .. 24 Terminology .. 16 Layout Guidelines... 24 Theory of Operation .. 18 Galvanical y Isolated Interface ... 25 Digital-to-Analog Converter .. 18 Outline Dimensions ... 26 Transfer Function ... 18 Ordering Guide .. 27 DAC Architecture ... 18
REVISION HISTORY 6/2017—Rev. B to Rev. C 3/2015—Rev. A to Rev. B
Changes to Features Section 1 .. 1 Changes to Table 4 and Figure 2 .. 6 Changes to Table 2 .. 3 Inserted Note 2 to Ordering Guide .. 27 Changes to Table 3 .. 5 Changes to Table 4 .. 6
6/2013—Rev. 0 to Rev. A
Changes to Table 5 and Figure 4 ... 7 Changes to Pin GAIN and Pin RSTSEL Descriptions; Table 7 . 10 Changes to Figure 5 .. 8 Changes to Table 6 .. 9
7/2012—Revision 0: Initial Version
Change to VLOGIC Pin Description and RESET Pin Description, Table 7 .. 9 Changes to Figure 12 and Figure 13 ... 11 Changes to Figure 14 to Figure 19 .. 12 Changes to Figure 20, Figure 22, and Figure 25 ... 13 Changes to Figure 32 .. 15 Changes to Table 8 .. 19 Changes to Readback Operation Section .. 21 Changes to Hardware Reset (RESET) Section .. 23 Changes to Ordering Guide .. 27 Rev. C | Page 2 of 27 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS AC CHARACTERISTICS TIMING CHARACTERISTICS DAISY-CHAIN AND READBACK TIMING CHARACTERISTICS Circuit and Timing Diagrams ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION DIGITAL-TO-ANALOG CONVERTER TRANSFER FUNCTION DAC ARCHITECTURE Output Amplifiers SERIAL INTERFACE Input Shift Register STANDALONE OPERATION WRITE AND UPDATE COMMANDS Write to Input Register n (Dependent on LDACB) Update DAC Register n with Contents of Input Register n Write to and Update DAC Channel n (Independent of LDACB) DAISY-CHAIN OPERATION READBACK OPERATION POWER-DOWN OPERATION LOAD DAC (HARDWARE LDACB PIN) Instantaneous DAC Updating (LDACB Held Low) Deferred DAC Updating (LDACB Is Pulsed Low) LDACB MASK REGISTER HARDWARE RESET (RESETB) RESET SELECT PIN (RSTSEL) APPLICATIONS INFORMATION MICROPROCESSOR INTERFACING AD5686/AD5684 TO ADSP-BF531 INTERFACE AD5686/AD5684 TO SPORT INTERFACE LAYOUT GUIDELINES GALVANICALLY ISOLATED INTERFACE OUTLINE DIMENSIONS ORDERING GUIDE