Datasheet AD5686, AD5684 (Analog Devices) - 5
| 制造商 | Analog Devices |
| 描述 | Quad, 16-/12-Bit nanoDAC+ with SPI Interface |
| 页数 / 页 | 27 / 5 — Data Sheet. AD5686/AD5684. AC CHARACTERISTICS. Table 3. Parameter2. Min. … |
| 修订版 | C |
| 文件格式/大小 | PDF / 757 Kb |
| 文件语言 | 英语 |
Data Sheet. AD5686/AD5684. AC CHARACTERISTICS. Table 3. Parameter2. Min. Typ. Max. Unit. Test Conditions/Comments3
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Data Sheet AD5686/AD5684 AC CHARACTERISTICS
VDD = 2.7 V to 5.5 V; VREF = 2.5 V; 1.62 V ≤ VLOGIC ≤ 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.1
Table 3. Parameter2 Min Typ Max Unit Test Conditions/Comments3
Output Voltage Settling Time AD5686 5 8 µs ¼ to ¾ scale settling to ±2 LSB AD5684 5 7 µs ¼ to ¾ scale settling to ±2 LSB Slew Rate 0.8 V/µs Digital-to-Analog Glitch Impulse 0.5 nV-sec 1 LSB change around major carry Digital Feedthrough 0.13 nV-sec Multiplying Bandwidth 500 kHz Digital Crosstalk 0.1 nV-sec Analog Crosstalk 0.2 nV-sec DAC-to-DAC Crosstalk 0.3 nV-sec Total Harmonic Distortion4 −80 dB At ambient, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz Output Noise Spectral Density 100 nV/√Hz DAC code = midscale, 10 kHz; gain = 2, internal reference enabled Output Noise 6 µV p-p 0.1 Hz to 10 Hz SNR 90 dB At ambient, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz SFDR 83 dB At ambient, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz SINAD 80 dB At ambient, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz 1 Guaranteed by design and characterization; not production tested. 2 See the Terminology section. 3 Temperature range is −40°C to +105°C, typical @ 25°C. 4 Digital y generated sine wave @ 1 kHz. Rev. C | Page 5 of 27 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS AC CHARACTERISTICS TIMING CHARACTERISTICS DAISY-CHAIN AND READBACK TIMING CHARACTERISTICS Circuit and Timing Diagrams ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION DIGITAL-TO-ANALOG CONVERTER TRANSFER FUNCTION DAC ARCHITECTURE Output Amplifiers SERIAL INTERFACE Input Shift Register STANDALONE OPERATION WRITE AND UPDATE COMMANDS Write to Input Register n (Dependent on LDACB) Update DAC Register n with Contents of Input Register n Write to and Update DAC Channel n (Independent of LDACB) DAISY-CHAIN OPERATION READBACK OPERATION POWER-DOWN OPERATION LOAD DAC (HARDWARE LDACB PIN) Instantaneous DAC Updating (LDACB Held Low) Deferred DAC Updating (LDACB Is Pulsed Low) LDACB MASK REGISTER HARDWARE RESET (RESETB) RESET SELECT PIN (RSTSEL) APPLICATIONS INFORMATION MICROPROCESSOR INTERFACING AD5686/AD5684 TO ADSP-BF531 INTERFACE AD5686/AD5684 TO SPORT INTERFACE LAYOUT GUIDELINES GALVANICALLY ISOLATED INTERFACE OUTLINE DIMENSIONS ORDERING GUIDE
Data Sheet AD5686/AD5684 AC CHARACTERISTICS
VDD = 2.7 V to 5.5 V; VREF = 2.5 V; 1.62 V ≤ VLOGIC ≤ 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.1
Table 3. Parameter2 Min Typ Max Unit Test Conditions/Comments3
Output Voltage Settling Time AD5686 5 8 µs ¼ to ¾ scale settling to ±2 LSB AD5684 5 7 µs ¼ to ¾ scale settling to ±2 LSB Slew Rate 0.8 V/µs Digital-to-Analog Glitch Impulse 0.5 nV-sec 1 LSB change around major carry Digital Feedthrough 0.13 nV-sec Multiplying Bandwidth 500 kHz Digital Crosstalk 0.1 nV-sec Analog Crosstalk 0.2 nV-sec DAC-to-DAC Crosstalk 0.3 nV-sec Total Harmonic Distortion4 −80 dB At ambient, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz Output Noise Spectral Density 100 nV/√Hz DAC code = midscale, 10 kHz; gain = 2, internal reference enabled Output Noise 6 µV p-p 0.1 Hz to 10 Hz SNR 90 dB At ambient, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz SFDR 83 dB At ambient, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz SINAD 80 dB At ambient, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz 1 Guaranteed by design and characterization; not production tested. 2 See the Terminology section. 3 Temperature range is −40°C to +105°C, typical @ 25°C. 4 Digital y generated sine wave @ 1 kHz. Rev. C | Page 5 of 27 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS AC CHARACTERISTICS TIMING CHARACTERISTICS DAISY-CHAIN AND READBACK TIMING CHARACTERISTICS Circuit and Timing Diagrams ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION DIGITAL-TO-ANALOG CONVERTER TRANSFER FUNCTION DAC ARCHITECTURE Output Amplifiers SERIAL INTERFACE Input Shift Register STANDALONE OPERATION WRITE AND UPDATE COMMANDS Write to Input Register n (Dependent on LDACB) Update DAC Register n with Contents of Input Register n Write to and Update DAC Channel n (Independent of LDACB) DAISY-CHAIN OPERATION READBACK OPERATION POWER-DOWN OPERATION LOAD DAC (HARDWARE LDACB PIN) Instantaneous DAC Updating (LDACB Held Low) Deferred DAC Updating (LDACB Is Pulsed Low) LDACB MASK REGISTER HARDWARE RESET (RESETB) RESET SELECT PIN (RSTSEL) APPLICATIONS INFORMATION MICROPROCESSOR INTERFACING AD5686/AD5684 TO ADSP-BF531 INTERFACE AD5686/AD5684 TO SPORT INTERFACE LAYOUT GUIDELINES GALVANICALLY ISOLATED INTERFACE OUTLINE DIMENSIONS ORDERING GUIDE