Datasheet AD9250 (Analog Devices) - 45

Data Sheet AD9250 OUTLINE DIMENSIONS DETAIL A 7.10 (JEDEC 95) 0.30 7.00 SQ 0.25 6.90 PIN 1 0.18 INDICATOR PIN 1 INDIC ATOR AREA OPTIONS 37 48 (SEE DETAIL A) 36 1 0.50 BSC 5.70 EXPOSED 5.60 SQ PAD 5.50 24 13 0.50 0.20 MIN TOP VIEW BOTTOM VIEW 0.40 0.30 5.50 REF 0.80 0.75 END VIEW FOR PROPER CONNECTION OF 0.05 MAX THE EXPOSED PAD, REFER TO 0.70 0.02 NOM THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS COPLANARITY SECTION OF THIS DATA SHEET. SEATING 0.08 PLANE 0.203 REF A 52 -2016- 044 -0 29 G K P COMPLIANT TO JEDEC STANDARDS MO-220-WKKD-4. 02-
Figure 64. 48-Lead Lead Frame Chip Scale Package [LFCSP] 7 mm × 7 mm Body and 0.75 mm Package Height (CP-48-13) Dimensions shown in millimeters
ORDERING GUIDE Model1 Temperature Range Package Description Package Option
AD9250BCPZ-170 −40°C to +85°C 48-Lead Lead Frame Chip Scale Package [LFCSP] CP-48-13 AD9250BCPZRL7-170 −40°C to +85°C 48-Lead Lead Frame Chip Scale Package [LFCSP] CP-48-13 AD9250-170EBZ −40°C to +85°C Evaluation Board with AD9250-170 AD9250BCPZ-250 −40°C to +85°C 48-Lead Lead Frame Chip Scale Package [LFCSP] CP-48-13 AD9250BCPZRL7-250 −40°C to +85°C 48-Lead Lead Frame Chip Scale Package [LFCSP] CP-48-13 AD9250-250EBZ −40°C to +85°C Evaluation Board with AD9250-250 1 Z = RoHS Compliant Part.
©2012–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10559-0-9/17(E)
Rev. E | Page 45 of 45 Document Outline Features Applications Functional Block Diagram Product Highlights Revision History General Description Specifications ADC DC Specifications ADC AC Specifications Digital Specifications Switching Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Equivalent Circuits Theory of Operation ADC Architecture Analog Input Considerations Input Common Mode Differential Input Configurations Voltage Reference Clock Input Considerations Nyquist Clock Input Options RF Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations Power Dissipation and Standby Mode Digital Outputs JESD204B Transmit Top Level Description JESD204B Overview JESD204B Synchronization Details CGS Phase ILAS Phase Data Transmission Phase Link Setup Parameters Disable Lanes Before Changing Configuration Select Quick Configuration Option Configure Detailed Options Check FCHK, Checksum of JESD204B Interface Parameters Additional Digital Output Configuration Options Re-Enable Lanes After Configuration Internal FIFO Timing Optimization Frame and Lane Alignment Monitoring and Correction Digital Outputs and Timing ADC Overrange and Gain Control ADC Overrange (OR) Gain Switching Fast Threshold Detection (FDA and FDB) DC Correction DC Correction Bandwidth DC Correction Readback DC Correction Freeze DC Correction (DCC) Enable Bits Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface SPI Accessible Features Memory Map Reading the Memory Map Register Table Open and Reserved Locations Default Values Logic Levels Channel-Specific Registers Memory Map Register Table Memory Map Register Description Applications Information Design Guidelines Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations VCM SPI Port SPI Initialization Sequence Outline Dimensions Ordering Guide