Datasheet AD9250 (Analog Devices) - 3

Data Sheet AD9250 REVISION HISTORY 9/2017—Rev. D to Rev. E 12/2013—Rev. A to Rev. B
Changes to Channel-Specific Registers Section . ... .. ... ... ... ... ... 36 Change to Features Section .. 1 Changes to Table 18 . ... .. ... ... ... ... ... .. .. ... ... ... ... ... .. .. ... .. 37 Change to Functional Block Diagram .. 1 Changes to Figure 63 and Table 19 . ... .. ... ... ... ... ... ... ... ... ... ... 43 Change to SYNCIN Input (SYNCINB+/SYNCINB−), Logic

Compliance Parameter, Table 3 ... 6
5/2017—Rev. C to Rev. D
Changes to Data Output Parameters, Table 4 ... 8 Change to Differential Output Voltage (VOD) Parameter, Table 3 .. 8 Changes to Figure 3 .. 9 Deleted Synchronization Section .. 26 Change to Figure 30, Added Figure 34 through Figure 37; Changes to Link Setup Parameters Section ... 26 Renumbered Sequential y .. 17 Deleted Clock Adjustment Register Writes Section ... 27 Changes to Table 9 .. 20 Added Internal FIFO Timing Optimization Section ... 28 Change to Figure 47 .. 21 Changes to Table 14 .. 30 Changes to JESD204B Overview Section .. 24 Changes to Channel-Specific Registers Section .. 36 Change to Configure Details Options Section .. 26 Deleted Transfer Register Map Section .. 37 Change to Check FCHK, Checksum of JESD204B Interface Changes to Table 18 .. 37 Parameters Section .. 27 Added SPI Initialization Sequence Section .. 42 Changes to Figure 54 .. 28 Added Figure 63 and Table 19; Renumbered Sequential y .. 43 Changes to Figure 57 and Figure 58 ... 29 Deleted JESD204B Configuration Section ... 44 Changes to Figure 59 and Figure 60 ... 30 Updated Outline Dimensions .. 45 Changes to Table 17 .. 36 Updated Outline Dimensions.. 42
1/2016—Rev. B to Rev. C
Moved Revision History Section ... 3
3/2013—Rev. 0 to Rev. A
Changes to Nyquist Clock Input Options .. 22 Changes to High Level Input Current and Low Level Input Added Synchronization Section .. 26 Current; Table 3 ... 6 Added Click Adjustment Register Writes Section .. 27 Changes to Table 4 .. 8 Changes to Link Setup Parameters Section ... 27 Changes to Figure 3 Caption ... 9 Change to Additional Digital Output Configuration Options Changes to Digital Inputs Description; Table 8 .. 11 Section .. 29 Changes to JESD204B Synchronization Details Section ... 24 Added Table 14, Renumbered Sequential y ... 30 Changes to Configure Detailed Options Section .. 25 Changes to Table 18 .. 38 Changes to Fast Threshold Detection (FDA and FDB) Section ... 30 Added JESD204B Configuration Section .. 43 Deleted Built-In Self-Test (BIST) and Output Test Section .. 32 Changes to Transfer Register Map Section .. 34 Changes to Table 17 .. 35
10/2012—Revision 0: Initial Version
Rev. E | Page 3 of 45 Document Outline Features Applications Functional Block Diagram Product Highlights Revision History General Description Specifications ADC DC Specifications ADC AC Specifications Digital Specifications Switching Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Equivalent Circuits Theory of Operation ADC Architecture Analog Input Considerations Input Common Mode Differential Input Configurations Voltage Reference Clock Input Considerations Nyquist Clock Input Options RF Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations Power Dissipation and Standby Mode Digital Outputs JESD204B Transmit Top Level Description JESD204B Overview JESD204B Synchronization Details CGS Phase ILAS Phase Data Transmission Phase Link Setup Parameters Disable Lanes Before Changing Configuration Select Quick Configuration Option Configure Detailed Options Check FCHK, Checksum of JESD204B Interface Parameters Additional Digital Output Configuration Options Re-Enable Lanes After Configuration Internal FIFO Timing Optimization Frame and Lane Alignment Monitoring and Correction Digital Outputs and Timing ADC Overrange and Gain Control ADC Overrange (OR) Gain Switching Fast Threshold Detection (FDA and FDB) DC Correction DC Correction Bandwidth DC Correction Readback DC Correction Freeze DC Correction (DCC) Enable Bits Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface SPI Accessible Features Memory Map Reading the Memory Map Register Table Open and Reserved Locations Default Values Logic Levels Channel-Specific Registers Memory Map Register Table Memory Map Register Description Applications Information Design Guidelines Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations VCM SPI Port SPI Initialization Sequence Outline Dimensions Ordering Guide