Datasheet Analog Devices AD9518-3ABCPZ-RL7 — 数据表

FUNCTIONAL BLOCK DIAGRAM
CP REF1
REFIN
REF2 CLK LF STATUS
MONITOR PLL Low phase noise, phase-locked loop (PLL)
On-chip VCO tunes from 1.75 GHz to 2.25 GHz
External VCO/VCXO to 2.4 GHz optional
1 differential or 2 single-ended reference inputs
Reference monitoring capability
Automatic revertive and manual reference
switchover/holdover modes
Accepts LVPECL, LVDS, or CMOS references to 250 MHz
Programmable delays in path to PFD
Digital or analog lock detect, selectable
3 pairs of 1.6 GHz LVPECL outputs
Each output pair shares a 1-to-32 divider with coarse
phase delay
Additive output jitter: 225 fs rms
Channel-to-channel skew paired outputs of 1600 MHz Section; Change to Table 21 . 22
Changes to Table 23 . 24
Change to Configuration and Register Settings Section . 25
Change to Phase Frequency Detector (PFD) Section . 26
Changes to Charge Pump (CP), On-Chip VCO, PLL …