Datasheet Analog Devices AD9520-5BCPZ — 数据表

12 LVPECL/24 CMOS Output
Clock Generator
AD9520-5 Data Sheet
FEATURES FUNCTIONAL BLOCK DIAGRAM
CP REFIN
REF2 CLK
CLK DIVIDER
AND MUXES ZERO
DELAY
LVPECL/
CMOS DIV/Φ OUT0
OUT1
OUT2 DIV/Φ OUT3
OUT4
OUT5 DIV/Φ OUT6
OUT7
OUT8 DIV/Φ OUT9
OUT10
OUT11 SPI/I2C CONTROL
PORT AND
DIGITAL LOGIC EEPROM AD9520-5 07239-001 REFIN STATUS
MONITOR PLL REF1 SWITCHOVER
AND MONITOR Low phase noise, phase-locked loop (PLL) …