Datasheet Analog Devices AD9572ACPZLVD-R7 — 数据表

Fiber Channel/Ethernet Clock Generator IC,
7 Clock Outputs
AD9572
FEATURES FUNCTIONAL BLOCK DIAGRAM
REFSEL XTAL
OSC CMOS
1 × 25MHz REFCLK LVPECL
OR LVDS DIVIDERS LPF THIRD
ORDER PFD/CP LDO VCO 2 × 106.25MHz LVPECL
OR LVDS
1 × 156.25MHz
LVPECL
OR LVDS DIVIDERS LPF
3RD ORDER LDO PFD/CP Fully integrated dual VCO/PLL cores
0.22 ps rms jitter from 0.637 MHz to 10 MHz at 106.25 MHz
0.19 ps rms jitter from 1.875 MHz to 20 MHz at 156.25 MHz
0.42 ps rms jitter from 12 kHz to 20 MHz at 125 MHz
Input crystal or clock frequency of 25 MHz
Preset divide ratios for 106.25 MHz, 156.25 MHz, 33.33 MHz,
100 MHz, and 125 MHz
Choice of LVPECL or LVDS output format
Integrated loop filters
Copy of reference clock output …