Ethernet Clock Generator, 10 Clock Outputs
AD9571
FEATURES FUNCTIONAL BLOCK DIAGRAM
REFSEL Fully integrated VCO/PLL core
0.17 ps rms jitter from 1.875 MHz to 20 MHz at 156.25 MHz
0.41 ps rms jitter from 12 kHz to 20 MHz at 125 MHz
Input crystal or clock frequency of 25 MHz
Preset divide ratios for 156.25 MHz, 33.33 MHz,100 MHz, and
125 MHz
Choice of LVPECL or LVDS output format
Integrated loop filter
6 copies of reference clock output
Rates configured via strapping pins
Space saving 6 mm × 6 mm 40-lead LFCSP
0.48 W power dissipation (LVDS operation)
0.69 W power dissipation (LVPECL operation)
3.3 V operation CMOS
XTAL
OSC
6 × 25MHz
REFCLK
PFD/CP 3RD-ORDER
LPF LVPECL OR …