Datasheet Analog Devices AD9525BCPZ-REEL7 — 数据表

Low Jitter Clock Generator
with Eight LVPECL Outputs
AD9525 Data Sheet
FEATURES FUNCTIONAL BLOCK DIAGRAM Integrated ultralow noise synthesizer
8 differential 3.6 GHz LVPECL outputs and 1 LVPECL SYNC
output or 2 CMOS SYNC outputs
2 differential reference inputs and 1 single-ended reference
input APPLICATIONS REFA AD9525 REFA
REFB PLL ÷S REFB SYNC_OUT
SYNC_OUT
OUT7 REFC OUT7
OUT6 LTE and multicarrier GSM base stations
Clocking high speed ADCs, DACs
ATE and high performance instrumentation
40/100 Gb/sec OTN line side clocking
Cable/DOCSIS CMTS clocking
Test and measurement OUT6
OUT5
OUT5
CLKIN OUT4
DIVIDERS OUT4 CLKIN OUT3
OUT3
OUT2 …