Datasheet Analog Devices AD9545 — 数据表

Quad Input, 10-Output, Dual DPLL/IEEE 1588,
1 pps Synchronizer and Jitter Cleaner AD9545 Data Sheet
FEATURES APPLICATIONS Dual DPLL synchronizes 1 Hz to 750 MHz physical layer
clocks, providing frequency translation with jitter
cleaning of noisy references
Complies with ITU-T G.8262 and Telcordia GR-253
Supports Telcordia GR-1244, ITU-T G.812, ITU-T G.813,
ITU-T G.823, ITU-T G.824, ITU-T G.825, and ITU-T G.8273.2
Continuous frequency monitoring and reference validation
for frequency deviation as low as 50 ppb (5 × 10−8)
Both DPLLs feature a 24-bit fractional divider with 24-bit
programmable modulus
Programmable digital loop filter bandwidth: 10−4 Hz to 1850 Hz
2 independent, programmable auxiliary NCOs (1 Hz to
65,535 Hz, resolution < 1.37 × 10−12 Hz), suitable for
IEEE 1588 Version 2 servo feedback in PTP applications
Automatic and manual holdover and reference switchover,
providing zero delay, hitless, or phase buildout operation
Programmable priority-based reference switching with
manual, automatic revertive, and automatic nonrevertive
modes supported
5 pairs of clock output pins with each pair useable as
differential LVDS/HCSL/CML or as 2 single-ended outputs …