Quad Input, Five-Output, Dual DPLL
Synchronizer and Adaptive Clock Translator AD9542 Data Sheet
FEATURES APPLICATIONS Dual DPLL synchronizes 2 kHz to 750 MHz physical layer
clocks providing frequency translation with jitter cleaning
of noisy references
Complies with ITU-T G.8262 and Telcordia GR-253
Supports Telcordia GR-1244, ITU-T G.812, G.813, G.823,
G.824, and G.825
Continuous frequency monitoring and reference validation
for frequency deviation as low as 50 ppb
Both DPLLs feature a 24-bit fractional divider with 24-bit
programmable modulus
Programmable digital loop filter bandwidth: 10−4 Hz to 1850 Hz
Automatic and manual holdover and reference switchover,
providing zero delay, hitless, or phase buildout operation
Programmable priority-based reference switching with
manual, automatic revertive, and automatic nonrevertive
modes supported
5 pairs of clock output pins with each pair useable as
differential LVDS/HCSL/CML or as 2 single-ended outputs
(1 Hz to 500 MHz)
2 differential or 4 single-ended input references
Crosspoint mux interconnects reference inputs to PLLs …