Datasheet Analog Devices LTC6952 — 数据表

LTC6952
Ultralow Jitter, 4.5GHz PLL
with 11 Outputs and JESD204B/JESD204C Support
FEATURES DESCRIPTION JESD204B/C, Subclass 1 SYSREF Signal Generation
nn Low Noise Integer-N PLL
nn Additive Output Jitter < 6fs
RMS
(Integration BW = 12kHz to 20MHz, f = 4.5GHz)
nn Additive Output Jitter 65fs
RMS (ADC SNR Method)
nn EZSync™, ParallelSync™ Multichip Synchronization
nn –229dBc/Hz Normalized In-Band Phase Noise Floor
nn –281dBc/Hz Normalized In-Band 1/f Noise
nn Eleven Independent, Low Noise Outputs with
Programmable Coarse Digital and Fine Analog Delays
nn Flexible Outputs Can Serve as Either a Device Clock
or SYSREF Signal
nn Reference Input Frequency up to 500MHz
nn LTC6952Wizard™ Software Design Tool Support
nn –40ºC to 125°C Operating Junction Temperature Range The LTC®6952 is a high performance, ultralow jitter,
JESD204B/C clock generation and distribution IC. It
includes a Phase Locked Loop (PLL) core, consisting of
a reference divider, phase-frequency detector (PFD) with …