FEATURES FUNCTIONAL BLOCK DIAGRAM 1.6 GHz differential clock input
3 programmable dividers
Divide-by in range from1 to 32
Phase select for coarse delay adjust
Three 800 MHz/250 MHz LVDS/CMOS clock outputs
Additive output jitter 300 fs rms
Time delays up to 11.6 ns
Device configured with 4-level logic pins
Space-saving, 32-lead LFCSP RSET VS GND AD9513 OUT0 /1 . /32 OUT0B
LVDS/CMOS CLK OUT1 /1 . /32 CLKB OUT1B
LVDS/CMOS SYNCB APPLICATIONS
Low jitter, low phase noise clock distribution
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
High performance wireless transceivers
High performance instrumentation
Broadband infrastructure
ATE LVDS/CMOS OUT2 ∆t /1 . /32 OUT2B SETUP LOGIC VREF S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 05595-001 Data Sheet 800 MHz Clock Distribution IC, Dividers,
Delay Adjust, Three Outputs
AD9513 Figure 1. GENERAL DESCRIPTION
The AD9513 features a three-output clock distribution IC in a
design that emphasizes low jitter and phase noise to maximize
data converter performance. Other applications with
demanding phase noise and jitter requirements also benefit …