Datasheet Analog Devices AD9515 — 数据表

Data Sheet 1.6 GHz Clock Distribution IC, Dividers,
Delay Adjust, Two Outputs
AD9515 FEATURES
1.6 GHz differential clock input
2 programmable dividers
Divide-by in range from1 to 32
Phase select for coarse delay adjust
1.6 GHz LVPECL clock output
Additive output jitter 225 fs rms
800 MHz/250 MHz LVDS/CMOS clock output
Additive output jitter 300 fs rms/290 fs rms
Time delays up to 10 ns
Device configured with 4-level logic pins
Space-saving, 32-lead LFCSP FUNCTIONAL BLOCK DIAGRAM
RSET VS GND AD9515 LVPECL
OUT0 /1 . /32
OUT0B
CLK
CLKB LVDS/CMOS
OUT1
∆t /1 . /32 OUT1B SYNCB APPLICATIONS
Low jitter, low phase noise clock distribution
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs …