Datasheet Texas Instruments DM505MRBABFR — 数据表

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SPRS976D – NOVEMBER 2016 – REVISED JULY 2017 DM505 SoC for Vision Analytics
15mm Package (ABF) Silicon Revision 2.0
1 Device Overview
1.1 Features 1 Architecture Designed for Vision Analytics
Applications Video and Image Processing Support
– Full-HD Video (1920 × 1080p, 60 fps)
– Video Input and Video Output Up to 2 C66x Floating-Point VLIW DSP
– Fully Object-Code Compatible With C67x and
C64x+
– Up to Thirty-two 16 × 16-Bit Fixed-Point
Multiplies per Cycle Up to 512kB of On-Chip L3 RAM Level 3 (L3) and Level 4 (L4) Interconnects Memory Interface (EMIF) Module
– Supports DDR3/DDR3L up to DDR-1066
– Supports DDR2 up to DDR-800
– Supports LPDDR2 up to DDR-667
– Up to 2GB Supported Dual ARM® Cortex®-M4 Image Processor (IPU) Vision AccelerationPac
– Embedded Vision Engine (EVE) Display Subsystem
– Display Controller With DMA Engine …