Datasheet Texas Instruments SN65LVDS104PWR — 数据表
| 制造商 | Texas Instruments |
| 系列 | SN65LVDS104 |
| 零件号 | SN65LVDS104PWR |
1：4 LVDS时钟扇出缓冲器16-TSSOP -40至85
数据表
SN65LVDS10x 4-Port LVDS and 4-Port TTL-to-LVDS Repeaters datasheet
PDF, 1.2 Mb, 修订版: G, 档案已发布: Dec 31, 2015
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价格
状态
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No |
打包
| Pin | 16 |
| Package Type | PW |
| Industry STD Term | TSSOP |
| JEDEC Code | R-PDSO-G |
| Package QTY | 2000 |
| Carrier | LARGE T&R |
| Device Marking | LVDS104 |
| Width (mm) | 4.4 |
| Length (mm) | 5 |
| Thickness (mm) | 1 |
| Pitch (mm) | .65 |
| Max Height (mm) | 1.2 |
| Mechanical Data | 下载 |
参数化
| Input Frequency(Max) | 400 MHz |
| Input Level | LVDS |
| Number of Outputs | 4 |
| Operating Temperature Range | -40 to 85 C |
| Output Frequency(Max) | 400 MHz |
| Output Level | LVDS |
| Package Group | TSSOP |
| Package Size: mm2:W x L | 16TSSOP: 32 mm2: 6.4 x 5(TSSOP) PKG |
| Rating | Catalog |
| VCC | 3.3 V |
| VCC Out | 3.3 V |
生态计划
| RoHS | Compliant |
应用须知
- DC-Coupling Between Differential LVPECL, LVDS, HSTL, and CMLPDF, 135 Kb, 档案已发布: Feb 19, 2003
- AC Coupling Between Differential LVPECL, LVDS, HSTL and CML (Rev. C)PDF, 417 Kb, 修订版: C, 档案已发布: Oct 17, 2007
This report provides a quick reference of ac-coupling techniques for interfacing between different logic levels. The four differential signaling levels found in this reportare low-voltage positive-referenced emitter coupled logic (LVPECL), low-voltage differential signals (LVDS), high-speed transceiver logic (HSTL), and current-modelogic (CML). From these four differential signaling levels, 16
模型线
系列: SN65LVDS104 (8)
制造商分类
- Semiconductors > Clock and Timing > Clock Buffers > Differential