Datasheet Texas Instruments OMAP5912 — 数据表

制造商Texas Instruments
系列OMAP5912

应用处理器

数据表

OMAP5912 Applications Processor datasheet
PDF, 2.5 Mb, 修订版: E, 档案已发布: Dec 19, 2005

价格

状态

OMAP5912ZDYOMAP5912ZDYAOMAP5912ZZG
Lifecycle StatusNRND (Not recommended for new designs)Obsolete (Manufacturer has discontinued the production of the device)NRND (Not recommended for new designs)
Manufacture's Sample AvailabilityNoNoNo

打包

OMAP5912ZDYOMAP5912ZDYAOMAP5912ZZG
N123
Pin289289289
Package TypeZDYZDYZZG
Industry STD TermBGABGABGA MICROSTAR
JEDEC CodeS-PBGA-NS-PBGA-NS-PBGA-N
Package QTY84160
CarrierJEDEC TRAY (5+1)EIAJ TRAY (5+1)
Device MarkingOMAP5912OMAP5912ZZG
Width (mm)191912
Length (mm)191912
Thickness (mm)1.731.73.9
Pitch (mm)11.5
Max Height (mm)2.322.321.2
Mechanical Data下载下载下载

生态计划

OMAP5912ZDYOMAP5912ZDYAOMAP5912ZZG
RoHSCompliantNot CompliantCompliant
Pb FreeNoYes

应用须知

  • DSP Instruction Cache Performance on the OMAP5912
    PDF, 47 Kb, 档案已发布: Feb 28, 2005
  • Enabling high-speed USB OTG functionality on TI DSPs
    PDF, 191 Kb, 档案已发布: May 18, 2007
  • OMAP591x: Tuning the System Memory Requirements of DSP/BIOS Link
    PDF, 251 Kb, 档案已发布: Mar 16, 2005
    The DSP/BIOSв„ў Link software has been designed to implement inter-processor communication between a host device and a DSP. For the case of OMAP591x devices, the default configuration of the DSP/BIOS Link software requires that 2MB of system memory is reserved for exclusive use by DSP/BIOS Link. The intention was to provide developers using DSP/BIOS Link plenty of memory to begin with and enab
  • Programming the DSP MMU in the OMAP5910 Device
    PDF, 476 Kb, 档案已发布: Oct 7, 2004
    The OMAP5910 device from Texas Instruments (TI) has a new dual-core architecture that is optimized for multimedia applications in a low-power environment. It couples two processorsВ—a TI-enhanced TI925T general-purpose processor and an ultralow-power TMS320C55xв„ў (C55xв„ў) digital signal processor (DSP)В—with a rich set of peripherals and powerful interfaces to achieve optimal per
  • Using the CSL to complement OS dispatcher in handling Cascaded Interrupts
    PDF, 299 Kb, 档案已发布: Nov 8, 2004
    This application report discusses how CSL's INTC module could be used to share the task of dispatching interrupts with the OS, in scenarios where the OS's interrupt dispatcher does not comprehend cascaded interrupts.The solution involves having the CSL dispatch the cascaded interrupts alone, while completely leaving the job of dispatching primary CPU interrupts to the OS.We also discuss an
  • High-Speed Interface Layout Guidelines (Rev. G)
    PDF, 814 Kb, 修订版: G, 档案已发布: Jul 27, 2017
    As modern bus interface frequencies scale higher, care must be taken in the printed circuit board (PCB) layout phase of a design to ensure a robust solution.

模型线

制造商分类

  • Semiconductors> Processors> Other Processors