Datasheet Texas Instruments OMAP5912ZZG — 数据表

制造商	Texas Instruments
系列	OMAP5912
零件号	OMAP5912ZZG

数据表

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PDF, 2.5 Mb, 修订版: E, 档案已发布: Dec 19, 2005

价格

状态

Lifecycle Status	NRND (Not recommended for new designs)
Manufacture's Sample Availability	No

打包

Pin	289	289	289
Package Type	ZZG	ZZG	ZZG
Industry STD Term	BGA MICROSTAR	BGA MICROSTAR	BGA MICROSTAR
JEDEC Code	S-PBGA-N	S-PBGA-N	S-PBGA-N
Package QTY	160	160	160
Carrier	EIAJ TRAY (5+1)	EIAJ TRAY (5+1)	EIAJ TRAY (5+1)
Device Marking	OMAP5912ZZG	TM	OMAP
Width (mm)	12	12	12
Length (mm)	12	12	12
Thickness (mm)	.9	.9	.9
Pitch (mm)	.5	.5	.5
Max Height (mm)	1.2	1.2	1.2
Mechanical Data	下载	下载	下载

生态计划

RoHS

Compliant

设计套件和评估模块

JTAG Emulators/ Analyzers: TMDSADP
Adaptive Clocking JTAG Emulator Adapters
Lifecycle Status: Active (Recommended for new designs)
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应用须知

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DSP Instruction Cache Performance on the OMAP5912
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Enabling high-speed USB OTG functionality on TI DSPs
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OMAP591x: Tuning the System Memory Requirements of DSP/BIOS Link
PDF, 251 Kb, 档案已发布: Mar 16, 2005
The DSP/BIOSв„ў Link software has been designed to implement inter-processor communication between a host device and a DSP. For the case of OMAP591x devices, the default configuration of the DSP/BIOS Link software requires that 2MB of system memory is reserved for exclusive use by DSP/BIOS Link. The intention was to provide developers using DSP/BIOS Link plenty of memory to begin with and enab
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Programming the DSP MMU in the OMAP5910 Device
PDF, 476 Kb, 档案已发布: Oct 7, 2004
The OMAP5910 device from Texas Instruments (TI) has a new dual-core architecture that is optimized for multimedia applications in a low-power environment. It couples two processorsВ—a TI-enhanced TI925T general-purpose processor and an ultralow-power TMS320C55xв„ў (C55xв„ў) digital signal processor (DSP)В—with a rich set of peripherals and powerful interfaces to achieve optimal per
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Using the CSL to complement OS dispatcher in handling Cascaded Interrupts
PDF, 299 Kb, 档案已发布: Nov 8, 2004
This application report discusses how CSL's INTC module could be used to share the task of dispatching interrupts with the OS, in scenarios where the OS's interrupt dispatcher does not comprehend cascaded interrupts.The solution involves having the CSL dispatch the cascaded interrupts alone, while completely leaving the job of dispatching primary CPU interrupts to the OS.We also discuss an
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High-Speed Interface Layout Guidelines (Rev. G)
PDF, 814 Kb, 修订版: G, 档案已发布: Jul 27, 2017
As modern bus interface frequencies scale higher, care must be taken in the printed circuit board (PCB) layout phase of a design to ensure a robust solution.

模型线

系列: OMAP5912 (3)

OMAP5912ZDY OMAP5912ZDYA OMAP5912ZZG

制造商分类

Semiconductors > Processors > Other Processors