Datasheet Texas Instruments DAC5674 — 数据表

制造商Texas Instruments
系列DAC5674
Datasheet Texas Instruments DAC5674

14位,400MSPS,2x-4x内插数模转换器(DAC)

数据表

14-Bit 400 MSPS 2x/4x Interpolating CommsDAC DAC datasheet
PDF, 1.3 Mb, 修订版: A, 档案已发布: Oct 4, 2005
从文件中提取

价格

状态

DAC5674IPHPDAC5674IPHPG4DAC5674IPHPR
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityNoNoNo

打包

DAC5674IPHPDAC5674IPHPG4DAC5674IPHPR
N123
Pin484848
Package TypePHPPHPPHP
Industry STD TermHTQFPHTQFPHTQFP
JEDEC CodeS-PQFP-GS-PQFP-GS-PQFP-G
Package QTY2502501000
CarrierJEDEC TRAY (10+1)JEDEC TRAY (10+1)LARGE T&R
Device MarkingDAC5674DAC5674DAC5674
Width (mm)777
Length (mm)777
Thickness (mm)111
Pitch (mm).5.5.5
Max Height (mm)1.21.21.2
Mechanical Data下载下载下载

参数化

Parameters / ModelsDAC5674IPHP
DAC5674IPHP
DAC5674IPHPG4
DAC5674IPHPG4
DAC5674IPHPR
DAC5674IPHPR
ArchitectureCurrent SourceCurrent SourceCurrent Source
DAC Channels111
InterfaceParallel CMOSParallel CMOSParallel CMOS
Interpolation2x,4x2x,4x2x,4x
Operating Temperature Range, C-40 to 85-40 to 85-40 to 85
Package GroupHTQFPHTQFPHTQFP
Package Size: mm2:W x L, PKG48HTQFP: 81 mm2: 9 x 9(HTQFP)48HTQFP: 81 mm2: 9 x 9(HTQFP)48HTQFP: 81 mm2: 9 x 9(HTQFP)
Power Consumption(Typ), mW435435435
RatingCatalogCatalogCatalog
Resolution, Bits141414
SFDR, dB767676
Sample / Update Rate, MSPS400400400

生态计划

DAC5674IPHPDAC5674IPHPG4DAC5674IPHPR
RoHSCompliantCompliantCompliant

应用须知

  • Interfacing op amps to high-speed DACs, Part 2: Current-sourcing DACs
    PDF, 617 Kb, 档案已发布: Oct 4, 2009
  • Passive Terminations for Current Output DACs
    PDF, 244 Kb, 档案已发布: Nov 10, 2008
    The correct implementation of the high-speed DAC output termination is critical to achieving the best possible performance. The typical application involves choosing the correct network to create the necessary dc bias levels and correct effective impedance load to keep the output voltage within the compliance levels. This ensures that the maximum output signal amplitude and optimum ac performance
  • Q4 2009 Issue Analog Applications Journal
    PDF, 1.5 Mb, 档案已发布: Oct 4, 2009
  • Wideband Complementary Current Output DAC Single-Ended Interface
    PDF, 597 Kb, 档案已发布: Jun 21, 2005
    High-speed digital-to-analog converters (DACs) most often use a transformer-coupled output stage. In applications where this configuration is not practical, a single op ampdifferential to single-ended stage has often been used. This application note steps through the exact design equations required to achieve gain matching from each output as well as a matched input impedance to each of the DA
  • Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
    PDF, 2.3 Mb, 档案已发布: Jun 2, 2008
    This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig
  • CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
    PDF, 424 Kb, 档案已发布: Jun 8, 2008
    Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers

模型线

制造商分类

  • Semiconductors> Data Converters> Digital-to-Analog Converters (DACs)> High Speed DACs (>10MSPS)