Datasheet Texas Instruments DAC5674IPHP — 数据表

制造商Texas Instruments
系列DAC5674
零件号DAC5674IPHP
Datasheet Texas Instruments DAC5674IPHP

14位,400MSPS,2x-4x内插数模转换器(DAC)48-HTQFP -40至85

数据表

14-Bit 400 MSPS 2x/4x Interpolating CommsDAC DAC datasheet
PDF, 1.3 Mb, 修订版: A, 档案已发布: Oct 4, 2005
从文件中提取

价格

状态

Lifecycle StatusActive (Recommended for new designs)
Manufacture's Sample AvailabilityNo

打包

Pin48
Package TypePHP
Industry STD TermHTQFP
JEDEC CodeS-PQFP-G
Package QTY250
CarrierJEDEC TRAY (10+1)
Device MarkingDAC5674
Width (mm)7
Length (mm)7
Thickness (mm)1
Pitch (mm).5
Max Height (mm)1.2
Mechanical Data下载

参数化

ArchitectureCurrent Source
DAC Channels1
InterfaceParallel CMOS
Interpolation2x,4x
Operating Temperature Range-40 to 85 C
Package GroupHTQFP
Package Size: mm2:W x L48HTQFP: 81 mm2: 9 x 9(HTQFP) PKG
Power Consumption(Typ)435 mW
RatingCatalog
Resolution14 Bits
SFDR76 dB
Sample / Update Rate400 MSPS

生态计划

RoHSCompliant

设计套件和评估模块

  • Evaluation Modules & Boards: DAC5674EVM
    DAC5674 14-Bit, 400-MSPS, 2x-4x Interpolating Digital-to-Analog Converter Evaluation Module
    Lifecycle Status: Active (Recommended for new designs)
  • Evaluation Modules & Boards: TSW2200EVM
    TSW2200 Low-Cost Portable Power Supply Evaluation Module
    Lifecycle Status: Active (Recommended for new designs)

应用须知

  • Interfacing op amps to high-speed DACs, Part 2: Current-sourcing DACs
    PDF, 617 Kb, 档案已发布: Oct 4, 2009
  • Passive Terminations for Current Output DACs
    PDF, 244 Kb, 档案已发布: Nov 10, 2008
    The correct implementation of the high-speed DAC output termination is critical to achieving the best possible performance. The typical application involves choosing the correct network to create the necessary dc bias levels and correct effective impedance load to keep the output voltage within the compliance levels. This ensures that the maximum output signal amplitude and optimum ac performance
  • Q4 2009 Issue Analog Applications Journal
    PDF, 1.5 Mb, 档案已发布: Oct 4, 2009
  • Wideband Complementary Current Output DAC Single-Ended Interface
    PDF, 597 Kb, 档案已发布: Jun 21, 2005
    High-speed digital-to-analog converters (DACs) most often use a transformer-coupled output stage. In applications where this configuration is not practical, a single op ampdifferential to single-ended stage has often been used. This application note steps through the exact design equations required to achieve gain matching from each output as well as a matched input impedance to each of the DA
  • Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
    PDF, 2.3 Mb, 档案已发布: Jun 2, 2008
    This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig
  • CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
    PDF, 424 Kb, 档案已发布: Jun 8, 2008
    Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers

模型线

系列: DAC5674 (3)

制造商分类

  • Semiconductors > Data Converters > Digital-to-Analog Converters (DACs) > High Speed DACs (>10MSPS)