Datasheet Texas Instruments CDC7005 — 数据表

制造商	Texas Instruments
系列	CDC7005

数据表

价格

状态

打包

参数化

Parameters / Models	CDC7005RGZ	CDC7005RGZR	CDC7005RGZRG4	CDC7005RGZT	CDC7005RGZTG4	CDC7005ZVA	CDC7005ZVAR	CDC7005ZVAT
Approx. Price (US$)	10.00 | 1ku
Divider Ratio	1 to 16	1 to 16	1 to 16	1 to 16	1 to 16	1 to 16	1 to 16	1 to 16
Input Level	LVCMOS (REF_CLK) LVPECL (VCXO_CLK)	LVCMOS (REF_CLK),LVPECL (VCXO_CLK)	LVCMOS (REF_CLK),LVPECL (VCXO_CLK)	LVCMOS (REF_CLK),LVPECL (VCXO_CLK)	LVCMOS (REF_CLK),LVPECL (VCXO_CLK)	LVCMOS (REF_CLK),LVPECL (VCXO_CLK)	LVCMOS (REF_CLK),LVPECL (VCXO_CLK)	LVCMOS (REF_CLK),LVPECL (VCXO_CLK)
No. of Outputs	5
Number of Inputs	1	1	1	1	1	1	1	1
Number of Outputs		5	5	5	5	5	5	5
Operating Temperature Range, C		-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85
Operating Temperature Range(C)	-40 to 85
Output Frequency(Max), MHz		800	800	800	800	800	800	800
Output Frequency(Max)(MHz)	800
Output Frequency(Min), MHz		10	10	10	10	10	10	10
Output Frequency(Min)(MHz)	10
Output Level	LVPECL	LVPECL	LVPECL	LVPECL	LVPECL	LVPECL	LVPECL	LVPECL
Package Group	VQFN	VQFN	VQFN	VQFN	VQFN	BGA	BGA	BGA
Package Size: mm2:W x L, PKG		48VQFN: 49 mm2: 7 x 7(VQFN)	48VQFN: 49 mm2: 7 x 7(VQFN)	48VQFN: 49 mm2: 7 x 7(VQFN)	48VQFN: 49 mm2: 7 x 7(VQFN)	64BGA: 64 mm2: 8 x 8(BGA)	64BGA: 64 mm2: 8 x 8(BGA)	64BGA: 64 mm2: 8 x 8(BGA)
Package Size: mm2:W x L (PKG)	48VQFN: 49 mm2: 7 x 7(VQFN)
Rating	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog
Special Features	OPAMP for Active Loop Filter Programmable Delay	OPAMP for Active Loop Filter,Programmable Delay	OPAMP for Active Loop Filter,Programmable Delay	OPAMP for Active Loop Filter,Programmable Delay	OPAMP for Active Loop Filter,Programmable Delay	OPAMP for Active Loop Filter,Programmable Delay	OPAMP for Active Loop Filter,Programmable Delay	OPAMP for Active Loop Filter,Programmable Delay
Supply Voltage(Max), V		3.6	3.6	3.6	3.6	3.6	3.6	3.6
Supply Voltage(Max)(V)	3.6
Supply Voltage(Min), V		3	3	3	3	3	3	3
Supply Voltage(Min)(V)	3

生态计划

应用须知

• 下载
  Open Loop Phase-Noise Performance of CDC7005 at Various Frequencies
  PDF, 353 Kb, 档案已发布: Dec 17, 2004
  This application brief presents phase-noise data taken on Texas Instruments CDC7005 jitter cleaner and synchronizer PLL. The phase noise performance of CDC7005 depends on thephase noise of the reference clock, the voltage-controlled crystal oscillator (VCXO) clock,and the CDC7005 itself. This applications brief shows the phase noise performance of the CDC7005 clock synthesizer at the most popula
• 下载
  Phase Noise (Jitter) Performance of CDC7005 With Different VCXOs (Rev. A)
  PDF, 1.3 Mb, 修订版: A, 档案已发布: Jul 19, 2005
• 下载
  Using The CDC7005 as a 1:5 PECL Buffer w/Programmable Divider Ratio (Rev. B)
  PDF, 85 Kb, 修订版: B, 档案已发布: Dec 15, 2009
• 下载
  General Guidelines: CDC7005 as a Clock Synthesizer and Jitter Cleaner (Rev. A)
  PDF, 207 Kb, 修订版: A, 档案已发布: Dec 16, 2003
• 下载
  Basics of the CDC7005 Hold Function
  PDF, 233 Kb, 档案已发布: Apr 13, 2006
  The CDC7005 is a high-performance clock synthesizer and jitter cleaner with implemented hold functionality. The hold functionality can be used for fail-safe operation if the reference clock is missing. This application report describes the basis, the advantages, and the limitations of the CDC7005 hold functionality. Additionally, a discrete realization of a simplified external hold function is sho
• 下载
  Implementing a CDC7005 Low Jitter Clock Solution for HIgh Speed High IF ADC Dev
  PDF, 627 Kb, 档案已发布: Jun 25, 2004
  Texas Instruments has introduced a family of devices suited to meet the demand for high-speed, high-IF sampling ADC devices like the ADS5500 ADC, capable of sampling at 125 MSPS. To realize the full potential of these high performance devices, it is imperative to provide an extremely low phase noise clock source. The CDC7005 clock distribution chip offers a real-world clocking solution to meet the

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制造商分类

• Semiconductors> Clock and Timing> Clock Jitter Cleaners> Single-Loop PLL