Datasheet Texas Instruments CDC7005RGZTG4 — 数据表

制造商Texas Instruments
系列CDC7005
零件号CDC7005RGZTG4
Datasheet Texas Instruments CDC7005RGZTG4

高性能,低相位噪声,低偏移时钟同步器,可将参考时钟同步至VCXO 48-VQFN -40至85

数据表

3.3-V High Performance Clock Synthesizer & Jitter Cleaner datasheet
PDF, 1.1 Mb, 修订版: L, 档案已发布: Jun 4, 2009
从文件中提取

价格

状态

Lifecycle StatusActive (Recommended for new designs)
Manufacture's Sample AvailabilityYes

打包

Pin48
Package TypeRGZ
Industry STD TermVQFN
JEDEC CodeS-PQFP-N
Package QTY250
CarrierSMALL T&R
Device MarkingCDC7005
Width (mm)7
Length (mm)7
Thickness (mm).9
Pitch (mm).5
Max Height (mm)1
Mechanical Data下载

参数化

Divider Ratio1 to 16
Input LevelLVCMOS (REF_CLK),LVPECL (VCXO_CLK)
Number of Inputs1
Number of Outputs5
Operating Temperature Range-40 to 85 C
Output Frequency(Max)800 MHz
Output Frequency(Min)10 MHz
Output LevelLVPECL
Package GroupVQFN
Package Size: mm2:W x L48VQFN: 49 mm2: 7 x 7(VQFN) PKG
RatingCatalog
Special FeaturesOPAMP for Active Loop Filter,Programmable Delay
Supply Voltage(Max)3.6 V
Supply Voltage(Min)3 V

生态计划

RoHSCompliant

设计套件和评估模块

  • Evaluation Modules & Boards: CDC7005QFN-EVM
    CDC7005 QFN Package Evaluation Module
    Lifecycle Status: Active (Recommended for new designs)
  • Evaluation Modules & Boards: CDC7005-EVM
    CDC7005 Evaluation Module
    Lifecycle Status: Active (Recommended for new designs)
  • Evaluation Modules & Boards: CDCM7005BGA-EVM
    CDCM7005 BGA Package Evaluation Module
    Lifecycle Status: Active (Recommended for new designs)
  • Evaluation Modules & Boards: CDCM7005QFN-EVM
    CDCM7005 QFN Package Evaluation Module
    Lifecycle Status: Active (Recommended for new designs)

应用须知

  • Open Loop Phase-Noise Performance of CDC7005 at Various Frequencies
    PDF, 353 Kb, 档案已发布: Dec 17, 2004
    This application brief presents phase-noise data taken on Texas Instruments CDC7005 jitter cleaner and synchronizer PLL. The phase noise performance of CDC7005 depends on thephase noise of the reference clock, the voltage-controlled crystal oscillator (VCXO) clock,and the CDC7005 itself. This applications brief shows the phase noise performance of the CDC7005 clock synthesizer at the most popula
  • Phase Noise (Jitter) Performance of CDC7005 With Different VCXOs (Rev. A)
    PDF, 1.3 Mb, 修订版: A, 档案已发布: Jul 19, 2005
  • Using The CDC7005 as a 1:5 PECL Buffer w/Programmable Divider Ratio (Rev. B)
    PDF, 85 Kb, 修订版: B, 档案已发布: Dec 15, 2009
  • General Guidelines: CDC7005 as a Clock Synthesizer and Jitter Cleaner (Rev. A)
    PDF, 207 Kb, 修订版: A, 档案已发布: Dec 16, 2003
  • Basics of the CDC7005 Hold Function
    PDF, 233 Kb, 档案已发布: Apr 13, 2006
    The CDC7005 is a high-performance clock synthesizer and jitter cleaner with implemented hold functionality. The hold functionality can be used for fail-safe operation if the reference clock is missing. This application report describes the basis, the advantages, and the limitations of the CDC7005 hold functionality. Additionally, a discrete realization of a simplified external hold function is sho
  • Implementing a CDC7005 Low Jitter Clock Solution for HIgh Speed High IF ADC Dev
    PDF, 627 Kb, 档案已发布: Jun 25, 2004
    Texas Instruments has introduced a family of devices suited to meet the demand for high-speed, high-IF sampling ADC devices like the ADS5500 ADC, capable of sampling at 125 MSPS. To realize the full potential of these high performance devices, it is imperative to provide an extremely low phase noise clock source. The CDC7005 clock distribution chip offers a real-world clocking solution to meet the

模型线

制造商分类

  • Semiconductors > Clock and Timing > Clock Jitter Cleaners > Single-Loop PLL