Datasheet Texas Instruments CD74AC112EE4 — 数据表

制造商Texas Instruments
系列CD74AC112
零件号CD74AC112EE4
Datasheet Texas Instruments CD74AC112EE4

具有设置和复位的16-PDIP -55至125的双路负缘触发JK触发器

数据表

CD54AC112, CD74AC112 datasheet
PDF, 857 Kb, 档案已发布: Jan 17, 2003
从文件中提取

价格

状态

Lifecycle StatusActive (Recommended for new designs)
Manufacture's Sample AvailabilityNo

打包

Pin16
Package TypeN
Industry STD TermPDIP
JEDEC CodeR-PDIP-T
Package QTY25
CarrierTUBE
Device MarkingCD74AC112E
Width (mm)6.35
Length (mm)19.3
Thickness (mm)3.9
Pitch (mm)2.54
Max Height (mm)5.08
Mechanical Data下载

参数化

Bits2
F @ Nom Voltage(Max)100 Mhz
ICC @ Nom Voltage(Max)0.04 mA
Output Drive (IOL/IOH)(Max)-24/24 mA
Package GroupPDIP
Package Size: mm2:W x LSee datasheet (PDIP) PKG
RatingCatalog
Schmitt TriggerNo
Technology FamilyAC
VCC(Max)5.5 V
VCC(Min)1.5 V
Voltage(Nom)3.3,5 V
tpd @ Nom Voltage(Max)11.1 ns

生态计划

RoHSCompliant
Pb FreeYes

应用须知

  • Power-Up Behavior of Clocked Devices (Rev. A)
    PDF, 34 Kb, 修订版: A, 档案已发布: Feb 6, 2015
  • Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc
    PDF, 43 Kb, 档案已发布: Apr 1, 1996
    Though low power consumption is a feature of CMOS devices sometimes this feature does not meet a designer?s system power supply constraints. Therefore a partial system power down or multiple Vcc supplies are used to meet the needs of the system. This document shows electrostatic discharge protection circuits. It also provides circuit and bus driver examples of partial system power down and curren

模型线

制造商分类

  • Semiconductors > Logic > Flip-Flop/Latch/Register > J-K Flip-Flop