Datasheet Texas Instruments 66AK2H12 — 数据表

制造商Texas Instruments
系列66AK2H12
Datasheet Texas Instruments 66AK2H12

多核DSP + ARM KeyStone II片上系统(SoC)

数据表

66AK2Hxx Multicore DSP+ARMВ® KeyStone II System-on-Chip (SoC) datasheet
PDF, 2.4 Mb, 修订版: F, 档案已发布: Jun 2, 2017
从文件中提取

价格

状态

66AK2H12BAAW266AK2H12BAAW2466AK2H12BAAWA266AK2H12BAAWA2466AK2H12BXAAW266AK2H12DAAW266AK2H12DAAW2466AK2H12DAAWA266AK2H12DAAWA2466AK2H12DXAAWA24
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityNoNoYesNoYesNoNoNoNoNo

打包

66AK2H12BAAW266AK2H12BAAW2466AK2H12BAAWA266AK2H12BAAWA2466AK2H12BXAAW266AK2H12DAAW266AK2H12DAAW2466AK2H12DAAWA266AK2H12DAAWA2466AK2H12DXAAWA24
N12345678910
Pin1517151715171517151715171517151715171517
Package TypeAAWAAWAAWAAWAAWAAWAAWAAWAAWAAW
Package QTY21212121212121212121
CarrierJEDEC TRAY (5+1)JEDEC TRAY (5+1)JEDEC TRAY (5+1)JEDEC TRAY (5+1)JEDEC TRAY (5+1)JEDEC TRAY (5+1)JEDEC TRAY (5+1)JEDEC TRAY (5+1)JEDEC TRAY (5+1)JEDEC TRAY (5+1)
Device Marking@2012 TI66AK2H12AAW66AK2H12AAWA1.2GHZ/1.4GHZ66AK2H12XAAW@2012 TI66AK2H12AAWA1.2GHZ66AK2H12AAW@2012 TI
Width (mm)40404040404040404040
Length (mm)40404040404040404040
Thickness (mm)3.073.073.073.073.073.073.073.073.073.07
Mechanical Data下载下载下载下载下载下载下载下载下载下载

参数化

Parameters / Models66AK2H12BAAW2
66AK2H12BAAW2
66AK2H12BAAW24
66AK2H12BAAW24
66AK2H12BAAWA2
66AK2H12BAAWA2
66AK2H12BAAWA24
66AK2H12BAAWA24
66AK2H12BXAAW2
66AK2H12BXAAW2
66AK2H12DAAW2
66AK2H12DAAW2
66AK2H12DAAW24
66AK2H12DAAW24
66AK2H12DAAWA2
66AK2H12DAAWA2
66AK2H12DAAWA24
66AK2H12DAAWA24
66AK2H12DXAAWA24
66AK2H12DXAAWA24
ARM CPU4 ARM Cortex-A154 ARM Cortex-A154 ARM Cortex-A154 ARM Cortex-A154 ARM Cortex-A154 ARM Cortex-A154 ARM Cortex-A154 ARM Cortex-A154 ARM Cortex-A154 ARM Cortex-A15
ARM MHz, Max.1200,14001200,14001200,14001200,14001200,14001200,14001200,14001200,14001200,14001200,1400
ApplicationsAutomation and Process,Avionics and Defense,Communications and Telecom,Consumer Electronics,Industrial,Medical,Security,SpaceAutomation and Process,Avionics and Defense,Communications and Telecom,Consumer Electronics,Industrial,Medical,Security,SpaceAutomation and Process,Avionics and Defense,Communications and Telecom,Consumer Electronics,Industrial,Medical,Security,SpaceAutomation and Process,Avionics and Defense,Communications and Telecom,Consumer Electronics,Industrial,Medical,Security,SpaceAutomation and Process,Avionics and Defense,Communications and Telecom,Consumer Electronics,Industrial,Medical,Security,SpaceAutomation and Process,Avionics and Defense,Communications and Telecom,Consumer Electronics,Industrial,Medical,Security,SpaceAutomation and Process,Avionics and Defense,Communications and Telecom,Consumer Electronics,Industrial,Medical,Security,SpaceAutomation and Process,Avionics and Defense,Communications and Telecom,Consumer Electronics,Industrial,Medical,Security,SpaceAutomation and Process,Avionics and Defense,Communications and Telecom,Consumer Electronics,Industrial,Medical,Security,SpaceAutomation and Process,Avionics and Defense,Communications and Telecom,Consumer Electronics,Industrial,Medical,Security,Space
DRAMDDR3,DDR3LDDR3,DDR3LDDR3,DDR3LDDR3,DDR3LDDR3,DDR3LDDR3,DDR3LDDR3,DDR3LDDR3,DDR3LDDR3,DDR3LDDR3,DDR3L
DSP8 C66x8 C66x8 C66x8 C66x8 C66x8 C66x8 C66x8 C66x8 C66x8 C66x
DSP MHz, Max.1200120012001200120012001200120012001200
EMAC4-port 1Gb Switch4-port 1Gb Switch4-port 1Gb Switch4-port 1Gb Switch4-port 1Gb Switch4-port 1Gb Switch4-port 1Gb Switch4-port 1Gb Switch4-port 1Gb Switch4-port 1Gb Switch
Hardware AcceleratorsPacket Accelerator,Security AcceleratorPacket Accelerator,Security AcceleratorPacket Accelerator,Security AcceleratorPacket Accelerator,Security AcceleratorPacket Accelerator,Security AcceleratorPacket Accelerator,Security AcceleratorPacket Accelerator,Security AcceleratorPacket Accelerator,Security AcceleratorPacket Accelerator,Security AcceleratorPacket Accelerator,Security Accelerator
I2C3333333333
On-Chip L2 Cache4096 KB (ARM Cluster),1024 KB (per C66x DSP core)4096 KB (ARM Cluster),1024 KB (per C66x DSP core)4096 KB (ARM Cluster),1024 KB (per C66x DSP core)4096 KB (ARM Cluster),1024 KB (per C66x DSP core)4096 KB (ARM Cluster),1024 KB (per C66x DSP core)4096 KB (ARM Cluster),1024 KB (per C66x DSP core)4096 KB (ARM Cluster),1024 KB (per C66x DSP core)4096 KB (ARM Cluster),1024 KB (per C66x DSP core)4096 KB (ARM Cluster),1024 KB (per C66x DSP core)4096 KB (ARM Cluster),1024 KB (per C66x DSP core)
Operating SystemsIntegrity,Linux,SYS/BIOS,VxWorksIntegrity,Linux,SYS/BIOS,VxWorksIntegrity,Linux,SYS/BIOS,VxWorksIntegrity,Linux,SYS/BIOS,VxWorksIntegrity,Linux,SYS/BIOS,VxWorksIntegrity,Linux,SYS/BIOS,VxWorksIntegrity,Linux,SYS/BIOS,VxWorksIntegrity,Linux,SYS/BIOS,VxWorksIntegrity,Linux,SYS/BIOS,VxWorksIntegrity,Linux,SYS/BIOS,VxWorks
Operating Temperature Range, C-40 to 100,0 to 85-40 to 100,0 to 85-40 to 100,0 to 85-40 to 100,0 to 85-40 to 100,0 to 85-40 to 100,0 to 85-40 to 100,0 to 85-40 to 100,0 to 85-40 to 100,0 to 85-40 to 100,0 to 85
Other On-Chip Memory6144 KB6144 KB6144 KB6144 KB6144 KB6144 KB6144 KB6144 KB6144 KB6144 KB
PCI/PCIe2 PCIe Gen22 PCIe Gen22 PCIe Gen22 PCIe Gen22 PCIe Gen22 PCIe Gen22 PCIe Gen22 PCIe Gen22 PCIe Gen22 PCIe Gen2
RatingCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalog
SPI3333333333
UART, SCI2222222222
USB1111111111

生态计划

66AK2H12BAAW266AK2H12BAAW2466AK2H12BAAWA266AK2H12BAAWA2466AK2H12BXAAW266AK2H12DAAW266AK2H12DAAW2466AK2H12DAAWA266AK2H12DAAWA2466AK2H12DXAAWA24
RoHSCompliantCompliantCompliantCompliantCompliantCompliantCompliantCompliantCompliantCompliant

应用须知

  • Keystone EDMA FAQ
    PDF, 1.3 Mb, 档案已发布: Sep 1, 2016
    This document is a collection of frequently asked questions (FAQs) on enhanced direct memory access (EDMA) on KeyStoneв„ў I (KS1) and KeyStone II (KS2) devices, along with useful collateral and software reference links.
  • Keystone II DDR3 Initialization
    PDF, 73 Kb, 档案已发布: Jan 26, 2015
    This application report provides a step-to-step initialization guide for the Keystone II device DDR3 SDRAM controller.
  • Throughput Performance Guide for KeyStone II Devices (Rev. B)
    PDF, 866 Kb, 修订版: B, 档案已发布: Dec 22, 2015
    This application report analyzes various performance measurements of the KeyStone II family of processors. It provides a throughput analysis of the various support peripherals to different end-points and memory access.
  • Keystone II DDR3 Debug Guide
    PDF, 143 Kb, 档案已发布: Oct 16, 2015
    This guide provides tools for use when debugging a failing DDR3 interface on a KeyStone II device.
  • Power Management of KS2 Device (Rev. C)
    PDF, 61 Kb, 修订版: C, 档案已发布: Jul 15, 2016
    This application report lists the steps to enable Class 0 Temperature Compensation (Class 0 TC) mode of SmartReflexв„ў Subsystem (SRSS) module available on such devices.
  • Hardware Design Guide for KeyStone II Devices
    PDF, 1.8 Mb, 档案已发布: Mar 24, 2014
  • Keystone NDK FAQ
    PDF, 54 Kb, 档案已发布: Oct 3, 2016
    This document is a collection of frequently asked questions (FAQ) on running the NDK examples on the KeyStoneв„ў family of devices.
  • SERDES Link Commissioning on KeyStone I and II Devices
    PDF, 138 Kb, 档案已发布: Apr 13, 2016
    The serializer-deserializer (SerDes) performs serial-to-parallel conversions on data received from a peripheral device and parallel-to-serial conversion on data received from the CPU. This application report explains the SerDes transmit and receive parameters tuning, tools and some debug techniques for TI Keystone I and Keystone II devices.
  • PCIe Use Cases for KeyStone Devices
    PDF, 320 Kb, 档案已发布: Dec 13, 2011
  • Optimizing Loops on the C66x DSP
    PDF, 585 Kb, 档案已发布: Nov 9, 2010
  • Clocking Design Guide for KeyStone Devices
    PDF, 1.5 Mb, 档案已发布: Nov 9, 2010
  • The C6000 Embedded Application Binary Interface Migration Guide (Rev. A)
    PDF, 20 Kb, 修订版: A, 档案已发布: Nov 10, 2010
    The C6000 compiler tools support a new ELF-based ABI named EABI. Prior to this time, the compiler only supported a single ABI, which is now named COFF ABI. The following compelling best-in-class features are available under the C6000 EABI:GeneralZero-init globals: “int gvar;” gets set to 0 before main runs.Dynamic linking: Add code to a running system.Native ROM
  • DDR3 Design Requirements for KeyStone Devices (Rev. B)
    PDF, 582 Kb, 修订版: B, 档案已发布: Jun 5, 2014
  • Multicore Programming Guide (Rev. B)
    PDF, 1.8 Mb, 修订版: B, 档案已发布: Aug 29, 2012
    As application complexity continues to grow, we have reached a limit on increasing performance by merely scaling clock speed. To meet the ever-increasing processing demand, modern System-On-Chip solutions contain multiple processing cores. The dilemma is how to map applications to multicore devices. In this paper, we present a programming methodology for converting applications to run on multicore
  • TI DSP Benchmarking
    PDF, 62 Kb, 档案已发布: Jan 13, 2016
    This application report provides benchmarks for the C674x DSP core, the C66x DSP core and the ARMВ®CortexВ®-A15 core. This document also shows how to reproduce these benchmarks on specific hardware platforms.
  • Thermal Design Guide for DSP and ARM Application Processors (Rev. A)
    PDF, 324 Kb, 修订版: A, 档案已发布: Aug 17, 2016
    This application report has been compiled to provide specific information and considerations regarding thermal design requirements for all DSP and ARM-based single and multi-core processors (collectively referred to as “processors”, “System-on-chip”, or “SoC”). The information contained within this document is intended to provide a minimum level of understanding with regards to the thermal require

模型线

制造商分类

  • Semiconductors> Processors> Digital Signal Processors> C6000 DSP + ARM Processors> 66AK2x