Datasheet Texas Instruments SM32C6712DGDPA16EP — 数据表

 

 

 
   
 



SGUS055 -SEPTEMBER 2004 D Controlled Baseline
D
D
D
D D D D D L1/L2 Memory Architecture -One Assembly/Test Site, One Fabrication
Site
Enhanced Diminishing Manufacturing
Sources (DMS) Support
Enhanced Product-Change Notification
Qualification Pedigree†
Low-Price/High-Performance Floating-Point
Digital Signal Processors (DSPs):
320C67xпЈЄ (SM320C6712, C6712C, C6712D)
-Eight 32-Bit Instructions/Cycle
-100-, 167-MHz Clock Rates
-10-, 6-ns Instruction Cycle Times
-600, 1000 MFLOPS
Advanced Very Long Instruction Word
(VLIW) C67xпЈЄ DSP Core …