Datasheet Texas Instruments V62/06639-02XE — 数据表
| 制造商 | Texas Instruments |
| 系列 | DAC5672-EP |
| 零件号 | V62/06639-02XE |
增强型产品双14位200Msps数模转换器48-TQFP -55至125
数据表
价格
状态
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No |
打包
| Pin | 48 |
| Package Type | PFB |
| Industry STD Term | TQFP |
| JEDEC Code | S-PQFP-G |
| Package QTY | 250 |
| Carrier | JEDEC TRAY (10+1) |
| Device Marking | DAC5672EP |
| Width (mm) | 7 |
| Length (mm) | 7 |
| Thickness (mm) | 1 |
| Pitch (mm) | .5 |
| Max Height (mm) | 1.2 |
| Mechanical Data | 下载 |
参数化
| Architecture | Current Source |
| DAC Channels | 2 |
| DNL(Max) | 3 +/-LSB |
| INL(Max) | 4 +/-LSB |
| Interface | Parallel CMOS |
| Operating Temperature Range | -55 to 125 C |
| Output Range Max. | 20 mA |
| Output Range Min. | 2 mA |
| Output Type | Current |
| Package Group | TQFP |
| Package Size: mm2:W x L | 48TQFP: 81 mm2: 9 x 9(TQFP) PKG |
| Power Consumption(Typ) | 330 mW |
| Rating | HiRel Enhanced Product |
| Reference: Type | Int |
| Resolution | 14 Bits |
| SFDR | 84 dB |
| SNR | 77 dB |
| Sample / Update Rate | 275 MSPS |
| Settling Time | 0.02 µs |
生态计划
| RoHS | Compliant |
设计套件和评估模块
- Evaluation Modules & Boards: TSW2200EVM
TSW2200 Low-Cost Portable Power Supply Evaluation Module
Lifecycle Status: Active (Recommended for new designs)
应用须知
- CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital ConvertersPDF, 424 Kb, 档案已发布: Jun 8, 2008
Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers - Phase Noise Performance and Jitter Cleaning Ability of CDCE72010PDF, 2.3 Mb, 档案已发布: Jun 2, 2008
This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig - High Speed Digital-to-Analog Converters Basics (Rev. A)PDF, 829 Kb, 修订版: A, 档案已发布: Oct 23, 2012
模型线
系列: DAC5672-EP (4)
- DAC5672MPFBEP DAC5672MPFBREP V62/06639-01XE V62/06639-02XE
制造商分类
- Semiconductors > Space & High Reliability > Data Converter > Digital to Analog Converters
其他名称:
V62/0663902XE, V62/06639 02XE