Datasheet AD797 (Analog Devices) - 11

制造商Analog Devices
描述Ultralow Distortion, Ultralow Noise Op Amp
页数 / 页19 / 11 — Data Sheet. AD797. THEORY OF OPERATION. BUFFER. VOUT. GAIN = gm × R1 × 5 …
修订版K
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Data Sheet. AD797. THEORY OF OPERATION. BUFFER. VOUT. GAIN = gm × R1 × 5 × 106. GAIN = g. m × R1 × A2 × A3. Q10. +IN. –IN. OUT. Q12. Q11. CURRENT

Data Sheet AD797 THEORY OF OPERATION BUFFER VOUT GAIN = gm × R1 × 5 × 106 GAIN = g m × R1 × A2 × A3 Q10 +IN –IN OUT Q12 Q11 CURRENT

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Data Sheet AD797 THEORY OF OPERATION
The architecture of the AD797 was developed to overcome The elimination of second-stage noise effects has the additional inherent limitations in previous amplifier designs. Previous benefit of making the low noise of the AD797 (<0.9 nV/√Hz) precision amplifiers used three stages to ensure high open-loop extend to beyond 1 MHz. This means new levels of perform- gain (see Figure 31) at the expense of additional frequency com- ance for sampled data and imaging systems. All of this pensation components. Slew rate and settling performance are performance as well as load drive in excess of 30 mA are made usually compromised, and dynamic performance is not adequate possible by the Analog Devices, Inc., advanced complementary beyond audio frequencies. As can be seen in Figure 31, the first bipolar (CB) process. stage gain is rolled off at high frequencies by the compensation Another unique feature of this circuit is that the addition of a network. Second stage noise and distortion then appears at the single capacitor, CN (see Figure 32), enables cancellation of input and degrade performance. The AD797, on the other hand, distortion due to the output stage. This can best be explained by uses a single ultrahigh gain stage to achieve dc as well as dynamic referring to a simplified representation of the AD797 using precision. As shown in the simplified schematic (Figure 32), idealized blocks for the different circuit elements (Figure 33). Node A, Node B, and Node C track the input voltage, forcing the operating points of all pairs of devices in the signal path to A single equation yields the open-loop transfer function of this match. By exploiting the inherent matching of devices fabricated on amplifier; solving it at Node B yields the same IC chip, high open-loop gain, CMRR, PSRR, and low VOUT  g m VOS are guaranteed by pairwise device matching (that is, NPN V CN IN  j  C   C j C  to NPN and PNP to PNP), not by an absolute parameter such as j A N A beta and the early voltage. where: gm is the transconductance of Q1 and Q2.
gm BUFFER VOUT
A is the gain of the output stage (~1).
R1 C1 R
V
L
OUT is voltage at the output. VIN is differential input voltage.
GAIN = gm × R1 × 5 × 106 a.
When CN is equal to CC, the ideal single-pole op amp response is attained:
C2
V g OUT m  V jC
g
IN
m A2 A3 BUFFER VOUT R1 C1 RL
In Figure 33, the terms of Node A, which include the properties of
R2
the output stage, such as output impedance and distortion, cancel 30
GAIN = g
0
m × R1 × A2 × A3
6- by simple subtraction. Therefore, the distortion cancellation does 84
b.
00 not affect the stability or frequency response of the amplifier. With Figure 31. Model of AD797 vs. That of a Typical Three-Stage Amplifier only 500 μA of output stage bias, the AD797 delivers a 1 kHz
V
sine wave into 60 Ω at 7 V rms with only 1 ppm of distortion.
CC R2 R3 CN R1 I5 I1 I2 CN Q4 Q3 Q10 Q7 A B A B Q9 VOUT +IN A V –IN OUT Q12 Q8 Q1 Q2 Q5 Q6 CC Q11 +IN –IN C CURRENT C Q1 Q2 MIRROR I6 C I1 I7 I4
1
1
-03 2
VSS
846 03 00
I3 C I4
6- 84 Figure 32. AD797 Simplified Schematic 00 Figure 33. AD797 Block Diagram This matching benefits not just dc precision, but, because it holds up dynamically, both distortion and settling time are also reduced. This single stage has a voltage gain of >5 × 106 and VOS < 80 μV, while at the same time providing a THD + noise of less than −120 dB and true 16-bit settling in less than 800 ns. Rev. K | Page 11 of 19 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION THERMAL RESISTANCE ESD CAUTION TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION NOISE AND SOURCE IMPEDANCE CONSIDERATIONS LOW FREQUENCY NOISE WIDEBAND NOISE BYPASSING CONSIDERATIONS THE NONINVERTING CONFIGURATION THE INVERTING CONFIGURATION DRIVING CAPACITIVE LOADS SETTLING TIME DISTORTION REDUCTION Differential Line Receiver A General-Purpose ATE/Instrumentation I/O Driver Ultrasound/Sonar Imaging Preamp Amorphous (Photodiode) Detector Professional Audio Signal Processing—DAC Buffers OUTLINE DIMENSIONS ORDERING GUIDE