Datasheet AD9680 (Analog Devices) - 12

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AD9680 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS – + R _S EF EF DD1 DD2 DD2 DD1 ND SR SR DD1 ND DD1 K– K+ DD1 DD2 DD2 DD1 AV AV AV AV AG SY SY AV AG AV CL CL AV AV AV AV 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AVDD1 1 48 AVDD1 AVDD1 2 47 AVDD1 AVDD2 3 46 AVDD2 AVDD3 4 45 AVDD3 VIN–A 5 44 VIN–B VIN+A 6 43 VIN+B AVDD3 7 AD9680 42 AVDD3 AVDD2 8 41 AVDD2 TOP VIEW AVDD2 9 (Not to Scale) 40 AVDD2 AVDD2 10 39 AVDD2 AVDD2 11 38 SPIVDD V_1P0 12 37 CSB SPIVDD 13 36 SCLK PDWN/STBY 14 35 SDIO DVDD 15 34 DVDD DGND 16 33 DGND 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 _A D D D D N D B– 0– 0+ 1– 1+ 2– 2+ 3– 3+ D N _B NB+ T T T T T T T T FD V IN U U U U V CI U U U U FD DRG DR NC N O O O O O O O O DR DRG Y Y D D D D D D D D S S R R R R SE SER SE SER SE SER SE SER NOTES 1. EXPOSED PAD. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE
05
PACKAGE PROVIDES THE GROUND REFENCE FOR AVDDx. THIS EXPOSED
-0
PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION.
11752 Figure 5. Pin Configuration (Top View)
Table 8. Pin Function Descriptions Pin No. Mnemonic Type Description
Power Supplies 0 EPAD Ground Exposed Pad. The exposed thermal pad on the bottom of the package provides the ground reference for AVDDx. This exposed pad must be connected to ground for proper operation. 1, 2, 47, 48, 49, 52, 55, 61, 64 AVDD1 Supply Analog Power Supply (1.25 V Nominal). 3, 8, 9, 10, 11, 39, 40, 41, AVDD2 Supply Analog Power Supply (2.5 V Nominal). 46, 50, 51, 62, 63 4, 7, 42, 45 AVDD3 Supply Analog Power Supply (3.3 V Nominal). 13, 38 SPIVDD Supply Digital Power Supply for SPI (1.8 V to 3.3 V). 15, 34 DVDD Supply Digital Power Supply (1.25 V Nominal). 16, 33 DGND Ground Ground Reference for DVDD. 18, 31 DRGND Ground Ground Reference for DRVDD. 19, 30 DRVDD Supply Digital Driver Power Supply (1.25 V Nominal). 56, 60 AGND1 Ground Ground Reference for SYSREF±. 57 AVDD1_SR1 Supply Analog Power Supply for SYSREF± (1.25 V Nominal). Analog 5, 6 VIN−A, VIN+A Input ADC A Analog Input Complement/True. 12 V_1P0 Input/DNC 1.0 V Reference Voltage Input/Do Not Connect. This pin is configurable through the SPI as a no connect or an input. Do not connect this pin if using the internal reference. Requires a 1.0 V reference voltage input if using an external voltage reference source. 44, 43 VIN−B, VIN+B Input ADC B Analog Input Complement/True. 53, 54 CLK+, CLK− Input Clock Input True/Complement. Rev. B | Page 12 of 91 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9680-1000 AD9680-820 AD9680-500 EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Differential Input Configurations Input Common Mode Analog Input Buffer Controls and SFDR Optimization Input Buffer Control Registers (0x018, 0x019, 0x01A, 0x935, 0x934, 0x11A) Absolute Maximum Input Swing VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Input Clock Divider Input Clock Divider ½ Period Delay Adjust Clock Fine Delay Adjust Clock Jitter Considerations Power-Down/Standby Mode Temperature Diode ADC OVERRANGE AND FAST DETECT ADC OVERRANGE FAST THRESHOLD DETECTION (FD_A AND FD_B) SIGNAL MONITOR SPORT OVER JESD204B DIGITAL DOWNCONVERTER (DDC) DDC I/Q INPUT SELECTION DDC I/Q OUTPUT SELECTION DDC GENERAL DESCRIPTION FREQUENCY TRANSLATION GENERAL DESCRIPTION Variable IF Mode 0 Hz IF (ZIF) Mode fS/4 Hz IF Mode Test Mode DDC NCO PLUS MIXER LOSS AND SFDR NUMERICALLY CONTROLLED OSCILLATOR Setting Up the NCO FTW and POW NCO Synchronization Mixer FIR FILTERS GENERAL DESCRIPTION HALF-BAND FILTERS HB4 Filter HB3 Filter HB2 Filter HB1 Filter DDC GAIN STAGE DDC COMPLEX TO REAL CONVERSION DDC EXAMPLE CONFIGURATIONS DIGITAL OUTPUTS INTRODUCTION TO THE JESD204B INTERFACE JESD204B OVERVIEW FUNCTIONAL OVERVIEW Transport Layer Data Link Layer Physical Layer JESD204B LINK ESTABLISHMENT Code Group Synchronization (CGS) and SYNCINB± Initial Lane Alignment Sequence (ILAS) User Data and Error Detection 8-Bit/10-Bit Encoder PHYSICAL LAYER (DRIVER) OUTPUTS Digital Outputs, Timing, and Controls De-Emphasis Phase-Locked Loop JESD204B TX CONVERTER MAPPING CONFIGURING THE JESD204B LINK Example 1: Full Bandwidth Mode Example 2: ADC with DDC Option (Two ADCs Plus Four DDCs) MULTICHIP SYNCHRONIZATION SYSREF± SETUP/HOLD WINDOW MONITOR TEST MODES ADC TEST MODES JESD204B BLOCK TEST MODES Transport Layer Sample Test Mode Interface Test Modes Data Link Layer Test Modes SERIAL PORT INTERFACE CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open and Reserved Locations Default Values Logic Levels Channel-Specific Registers SPI Soft Reset MEMORY MAP REGISTER TABLE APPLICATIONS INFORMATION POWER SUPPLY RECOMMENDATIONS EXPOSED PAD THERMAL HEAT SLUG RECOMMENDATIONS AVDD1_SR (PIN 57) AND AGND (PIN 56 AND PIN 60) OUTLINE DIMENSIONS ORDERING GUIDE