Datasheet RX74N (Renesas) - 7

link to page 11 RX74N Group 1. Overview
Table 1.1 Outline of Specifications (6/10) Classification Module/Function Description
Timers GPTW port output Various types of request to stop output from general PWM timers (GPTWs) are available. enable (POEGd) Stopping output in response to detecting the input level on the GTETRGx pin Stopping output in response to an output stopping signal from the GPTW Stopping output in response to detecting the stopping of oscillation, or to requests by software Stopping output in response to detecting the input level or an edge on the POEG pin 8-bit timer (TMRa) (8 bits × 2 channels) × 2 units Select from among seven internal clock signals (PCLKB/1, PCLKB/2, PCLKB/8, PCLKB/32, PCLKB/64, PCLKB/1024, PCLKB/8192) and one external clock signal Capable of output of pulse trains with desired duty cycles or of PWM signals The 2 channels of each unit can be cascaded to create a 16-bit timer Capable of generating baud-rate clocks for RSCI Event linking by the ELC Compare match timer (16 bits × 2 channels) × 2 units (CMT) Select from among four internal clock signals (PCLKB/8, PCLKB/32, PCLKB/128, PCLKB/512) Compare match timer W (32 bits × 1 channel) × 2 units (CMTW) Compare-match, input-capture input, and output-comparison output are available. Select from among four internal clock signals (PCLKB/8, PCLKB/32, PCLKB/128, PCLKB/512) Interrupt requests can be output in response to compare-match, input-capture, and output-comparison events. Event linking by the ELC Realtime clock (RTCBb) Clock sources: Low-speed on-chip oscillator, sub-clock Selection of the 32-bit binary count in time count/second unit possible Clock and calendar functions Interrupt sources: Alarm interrupt, periodic interrupt, and carry interrupt Battery backup operation Time-capture facility for three values Event linking by the ELC Watchdog timer (WDTA) 14 bits × 1 channel Select from among 6 counter-input clock signals (PCLKB/4, PCLKB/64, PCLKB/128, PCLKB/512, PCLKB/2048, PCLKB/8192) Event linking by the ELC Independent watchdog 14 bits × 1 channel timer (IWDTa) Counter-input clock: Low-speed on-chip oscillator (IWDT-dedicated clock) Dedicated clock/1, dedicated clock/16, dedicated clock/32, dedicated clock/64, dedicated clock/128, dedicated clock/256 Window function: The positions where the window starts and ends are specifiable (the window defines the timing with which refreshing is enabled and disabled). Event linking by the ELC Operation in the deep software standby mode 1 is possible. Communications Ethernet module One channel (one port) functions (ESWM) Transfer at 10, 100, or 1000 Mbps Full- and half-duplex modes Detection of Magic PacketsTM*1 or output of a “Wake-On-LAN” signal (WOL) Management frame transmission/reception with PHY-LSI compliant with the following specifications: MII (Media-Independent Interface), RMII (Reduced Media-Independent Interface), GMII (Gigabit Media-Independent Interface), and RGMII (Reduced Gigabit Media-Independent Interface) Support for MII MAC-to-MAC connection Two gPTP channels R01DS0434EJ0110 Rev.1.10 Page 7 of 285 Jul 31, 2026 Document Outline Features 1. Overview 1.1 Outline of Specifications 1.2 List of Products 1.3 Block Diagram 1.4 Pin Functions 1.5 Pin Assignments 1.5.1 320-Pin LFBGA 1.5.2 224-Pin LFBGA 1.5.3 176-Pin LFBGA 1.5.4 176-Pin LFQFP 1.5.5 144-Pin LFQFP 1.5.6 100-Pin LFQFP 1.6 List of Pin and Pin Functions 1.6.1 320-Pin LFBGA 1.6.2 224-Pin LFBGA 1.6.3 176-Pin LFBGA 1.6.4 176-Pin LFQFP 1.6.5 144-Pin LFQFP 1.6.6 100-Pin LFQFP 2. Electrical Characteristics 2.1 Test Conditions 2.1.1 Maximum and Minimum Values (Max./Min.) 2.1.2 Typical Values (Typ.) 2.2 Absolute Maximum Ratings 2.3 Recommended Operating Conditions 2.4 DC Characteristics 2.4.1 Characteristics of the Input Voltage of the I/O Pins 2.4.2 Characteristics of the Output Voltage of the I/O Pins 2.4.3 Characteristics of the Other I/O Pins 2.4.4 Operating and Standby Currents 2.4.4.1 Operating and Standby Currents for Product Part No. R5K574Nxy4xx (y = A, B, C, D) 2.4.4.2 Operating and Standby Currents for Product Part No. R5K574Nxy4xx (y = E, F) 2.4.4.3 Currents in Deep Software Standby Mode 2.4.4.4 Other Operating Currents 2.4.4.5 Permissible Output Currents 2.4.5 Thermal Characteristics 2.4.5.1 Thermal Resistance Value 2.4.5.2 Supply Currents for the Peripheral Functions 2.4.5.3 Example of Calculation of Ta 2.4.6 VCC Rising and Falling Slopes and Ripple Frequency 2.5 AC Characteristics 2.5.1 Operating Frequency 2.5.2 Clock Timing 2.5.3 Reset Timing 2.5.4 Timing of Return from Low Power Consumption Modes 2.5.5 Control Signal Timing 2.5.6 Bus Timing 2.5.7 Timing of On-Chip Peripheral Modules 2.5.7.1 I/O Port 2.5.7.2 TMR 2.5.7.3 CMTW 2.5.7.4 POEG 2.5.7.5 GPTW 2.5.7.6 RSCI 2.5.7.7 RSPIA 2.5.7.8 XSPI 2.5.7.9 RIICHS 2.5.7.10 RI3C 2.5.7.11 SSIE 2.5.7.12 SD/MMC Host Interface 2.5.7.13 PDC 2.5.7.14 HRPWM 2.5.7.15 CANFD/CANFDG 2.5.7.16 ESWM 2.5.7.17 PDMIF 2.5.7.18 PCIF 2.5.7.19 PIO 2.5.7.20 A/D Converter Trigger 2.5.7.21 CAC 2.6 USB Characteristics 2.6.1 USB Timing 2.6.2 USBHS Timing 2.7 A/D Conversion Characteristics 2.7.1 Analog Input Voltage Range 2.7.2 Common Characteristics of the 16-Bit A/D Converter 2.7.3 SAR Mode Characteristics 2.7.4 Common Characteristics of Oversampling Mode and Hybrid Mode 2.7.5 Oversampling Mode Characteristics 2.7.6 Hybrid Mode Characteristics 2.8 D/A Conversion Characteristics 2.9 Temperature Sensor Characteristics 2.10 Power-on Reset Circuit and Voltage Detection Circuit Characteristics 2.11 Core Voltage Monitoring Reset Characteristics 2.12 Oscillation Stop Detection Timing 2.13 External VDD Timing Characteristics 2.14 Battery Backup Function Characteristics 2.15 MRAM Characteristics 2.15.1 Code MRAM Characteristics 2.15.2 Option-Setting Memory (MRAM Area) Characteristics 2.15.3 Option-Setting Memory (OTP Area with ECC) Characteristics 2.15.4 Option-Setting Memory (OTP Area without ECC) Characteristics 2.15.5 MACI Command Characteristics 2.15.6 W-HUK Zeroization Characteristics 2.15.7 MRAM Magnetic Field Resistance Characteristics 2.15.8 Data MRAM Characteristics 2.16 Boundary Scan 2.17 Usage Note 2.17.1 Connecting VCL Capacitor and Bypass Capacitors Appendix 1. Package Dimensions REVISION HISTORY General Precautions in the Handling of Microprocessing Unit and Microcontroller Unit Products Notice