Preliminary Datasheet AVR32EB14, AVR32EB20, AVR32EB28, AVR32EB32 (Microchip) - 6

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AVR32EB14/20/28/32 Preliminary Data Sheet Table of Contents
Introduction...1 Family Overview..1 Memory Overview... 2 Peripheral Overview..2 Security Concept..3 Features... 4 1. Block Diagram..12 2. Pinout... 13 2.1. 14-Pin SOIC and TSSOP... 13 2.2. 20-Pin SSOP.. 13 2.3. 28-Pin SPDIP and SSOP... 14 2.4. 28-Pin VQFN..15 2.5. 32-Pin VQFN and TQFP..16 3. I/O Multiplexing and Considerations.. 17 3.1. I/O Multiplexing..17 4. Hardware Guidelines.. 19 4.1. General Guidelines.. 19 4.2. Connection for Power Supply...19 4.3. Connection for RESET..20 4.4. Connection for UPDI Programming...21 4.5. Connecting External Crystal Oscillators.. 22 4.6. Connection for External Voltage Reference... 23 5. Power Domains... 25 6. Conventions... 26 6.1. Numerical Notation... 26 6.2. Memory Size and Type.. 26 6.3. Frequency and Time.. 26 6.4. Registers and Bits.. 26 6.5. ADC Parameter Definitions...28 7. AVR® CPU.. 30 7.1. Features.. 30 7.2. Overview... 30 7.3. Architecture.. 30 7.4. Functional Description.. 32 7.5. Register Summary ...37 7.6. Register Description.. 37 8. Memories... 41 8.1. Overview... 41 8.2. Memory Map.. 41  Preliminary Data Sheet DS40002615A - 6 © 2024 Microchip Technology Inc. and its subsidiaries Document Outline Introduction Family Overview 1.  Memory Overview 2.  Peripheral Overview Security Concept Features Table of Contents 1.  Block Diagram 2.  Pinout 2.1.  14-Pin SOIC and TSSOP 2.2.  20-Pin SSOP 2.3.  28-Pin SPDIP and SSOP 2.4.  28-Pin VQFN 2.5.  32-Pin VQFN and TQFP 3.  I/O Multiplexing and Considerations 3.1.  I/O Multiplexing 4.  Hardware Guidelines 4.1.  General Guidelines 4.1.1.  Special Consideration for Packages with Center Pad 4.2.  Connection for Power Supply 4.2.1.  Digital Power Supply 4.3.  Connection for RESET 4.4.  Connection for UPDI Programming 4.4.1.  UPDI Connection v1 4.4.2.  UPDI Connection v2 4.5.  Connecting External Crystal Oscillators 4.5.1.  Connection for XTAL32K (External 32.768 kHz Crystal Oscillator) 4.6.  Connection for External Voltage Reference 5.  Power Domains 6.  Conventions 6.1.  Numerical Notation 6.2.  Memory Size and Type 6.3.  Frequency and Time 6.4.  Registers and Bits 6.4.1.  Addressing Registers from Header Files 6.5.  ADC Parameter Definitions 7.  AVR® CPU 7.1.  Features 7.2.  Overview 7.3.  Architecture 7.3.1.  Arithmetic Logic Unit (ALU) 7.3.1.1.  Hardware Multiplier 7.4.  Functional Description 7.4.1.  Program Flow 7.4.2.  Instruction Execution Timing 7.4.3.  Status Register 7.4.4.  Stack and Stack Pointer 7.4.5.  Register File 7.4.5.1.  The X-, Y-, and Z-Registers 7.4.6.  Configuration Change Protection (CCP) 7.4.6.1.  Sequence for Write Operation to Configuration Change Protected I/O Registers 7.4.6.2.  Sequence for Execution of Self-Programming 7.4.7.  On-Chip Debug Capabilities 7.5.  Register Summary 7.6.  Register Description 7.6.1.  Configuration Change Protection 7.6.2.  Stack Pointer 7.6.3.  Status Register 8.  Memories 8.1.  Overview 8.2.  Memory Map 8.3.  In-System Reprogrammable Flash Program Memory 8.4.  Program and Debug Interface Disable (PDID) 8.5.  SRAM Data Memory 8.6.  EEPROM Data Memory 8.7.  SIGROW - Signature Row 8.7.1.  Signature Row Summary 8.7.2.  Signature Row Description 8.7.2.1.  Device ID n 8.7.2.2.  Temperature Sensor Calibration n 8.7.2.3.  Serial Number Byte n 8.8.  USERROW - User Row 8.9.  BOOTROW - Boot Row 8.10.  FUSE - Configuration and User Fuses 8.10.1.  Fuse Summary 8.10.2.  Fuse Description 8.10.2.1.  Watchdog Configuration 8.10.2.2.  Brown-Out Detector Configuration 8.10.2.3.  Oscillator Configuration 8.10.2.4.  System Configuration 0 8.10.2.5.  System Configuration 1 8.10.2.6.  Code Size 8.10.2.7.  Boot Size 8.10.2.8.  UPDI Protection 8.11.  LOCK - Memory Sections Access Protection 8.11.1.  Lock Summary 8.11.2.  Lock Description 8.11.2.1.  Lock Key 8.12.  I/O Memory 8.12.1.  Accessing 16-Bit Registers 8.12.2.  Accessing 24-and 32-Bit Registers 9.  GPR - General Purpose Registers 9.1.  Register Summary 9.2.  Register Description 9.2.1.  General Purpose Register n 10.  Peripherals and Architecture 10.1.  Peripheral Address Map 10.2.  Interrupt Vector Mapping 10.3.  SYSCFG - System Configuration 10.3.1.  Register Summary 10.3.2.  Register Description 10.3.2.1.  Device Revision ID 11.  NVMCTRL - Nonvolatile Memory Controller 11.1.  Features 11.2.  Overview 11.2.1.  Block Diagram 11.3.  Functional Description 11.3.1.  Memory Organization 11.3.1.1.  Flash 11.3.1.1.1.  Physical Sections 11.3.1.1.2.  Logical Sections 11.3.1.1.3.  Flash Access Protections 11.3.1.2.  EEPROM 11.3.1.3.  User Row 11.3.1.4.  Boot Row 11.3.1.5.  Fuses 11.3.1.6.  Signature Row 11.3.2.  Memory Access 11.3.2.1.  Read 11.3.2.2.  Page Buffer Load 11.3.2.3.  Programming 11.3.2.4.  Command Modes 11.3.2.4.1.  Page Write Command 11.3.2.4.2.  Page Erase Command 11.3.2.4.3.  Flash Multi-Page Erase Mode 11.3.2.4.4.  Page Erase/Write Operation 11.3.2.4.5.  Page Buffer Clear Commands 11.3.2.4.6.  EEPROM Erase Command 11.3.3.  Preventing Flash/EEPROM Corruption 11.3.4.  Interrupts 11.3.5.  Sleep Mode Operation 11.3.6.  Configuration Change Protection 11.4.  Register Summary 11.5.  Register Description 11.5.1.  Control A 11.5.2.  Control B 11.5.3.  Control C 11.5.4.  Interrupt Control 11.5.5.  Interrupt Flags 11.5.6.  Status 11.5.7.  Data 11.5.8.  Address 12.  CLKCTRL - Clock Controller 12.1.  Features 12.2.  Overview 12.2.1.  Block Diagram - CLKCTRL 12.2.2.  Signal Description 12.3.  Functional Description 12.3.1.  Initialization 12.3.2.  Main Clock Selection and Prescaler 12.3.3.  Main Clock After Reset 12.3.4.  Clock Sources 12.3.4.1.  Internal Oscillators 12.3.4.1.1.  Internal High-Frequency Oscillator (OSCHF) 12.3.4.1.2.  32.768 kHz Oscillator (OSC32K) 12.3.4.2.  External Clock Sources 12.3.4.2.1.  32.768 kHz Crystal Oscillator (XOSC32K) 12.3.5.  Phase-Locked Loop (PLL) 12.3.6.  Timebase 12.3.7.  Manual Tuning and Autotune 12.3.8.  Sleep Mode Operation 12.3.9.  Configuration Change Protection 12.4.  Register Summary 12.5.  Register Description 12.5.1.  Main Clock Control A 12.5.2.  Main Clock Control B 12.5.3.  Main Clock Status 12.5.4.  Timebase 12.5.5.  Internal High-Frequency Oscillator Control A 12.5.6.  Internal High-Frequency Oscillator Frequency Tune 12.5.7.  Internal 32.768 kHz Oscillator Control A 12.5.8.  External 32.768 kHz Crystal Oscillator Control A 12.5.9.  PLL Control A 12.5.10.  PLL Control B 13.  SLPCTRL - Sleep Controller 13.1.  Features 13.2.  Overview 13.2.1.  Block Diagram 13.3.  Functional Description 13.3.1.  Initialization 13.3.2.  Operation 13.3.2.1.  Sleep Modes 13.3.2.2.  Wake-up Time 13.3.3.  Debug Operation 13.4.  Register Summary 13.5.  Register Description 13.5.1.  Control A 14.  RSTCTRL - Reset Controller 14.1.  Features 14.2.  Overview 14.2.1.  Block Diagram 14.2.2.  Signal Description 14.3.  Functional Description 14.3.1.  Initialization 14.3.2.  Operation 14.3.2.1.  Reset Sources 14.3.2.1.1.  Power-on Reset (POR) 14.3.2.1.2.  Brown-out Detector (BOD) Reset 14.3.2.1.3.  External Reset 14.3.2.1.4.  Watchdog Reset 14.3.2.1.5.  Software Reset (SWRST) 14.3.2.1.6.  Unified Program and Debug Interface (UPDI) Reset 14.3.2.1.7.  High Voltage (HV) Pulse 14.3.2.1.8.  Domains Affected By Reset 14.3.2.2.  Reset Time 14.3.3.  Sleep Mode Operation 14.3.4.  Configuration Change Protection 14.4.  Register Summary 14.5.  Register Description 14.5.1.  Reset Flag Register 14.5.2.  Software Reset Register 15.  CPUINT - CPU Interrupt Controller 15.1.  Features 15.2.  Overview 15.2.1.  Block Diagram 15.3.  Functional Description 15.3.1.  Initialization 15.3.2.  Operation 15.3.2.1.  Enabling, Disabling and Resetting 15.3.2.2.  Interrupt Vector Locations 15.3.2.3.  Interrupt Response Time 15.3.2.4.  Interrupt Priority 15.3.2.4.1.  Non-Maskable Interrupts 15.3.2.4.2.  High-Priority Interrupt 15.3.2.4.3.  Normal-Priority Interrupts 15.3.2.4.3.1.  Static Scheduling 15.3.2.4.3.2.  Modified Static Scheduling 15.3.2.4.3.3.  Round Robin Scheduling 15.3.2.5.  Compact Vector Table 15.3.3.  Debug Operation 15.3.4.  Configuration Change Protection 15.4.  Register Summary 15.5.  Register Description 15.5.1.  Control A 15.5.2.  Status 15.5.3.  Interrupt Priority Level 0 15.5.4.  Interrupt Vector with Priority Level 1 16.  EVSYS - Event System 16.1.  Features 16.2.  Overview 16.2.1.  Block Diagram 16.2.2.  Signal Description 16.3.  Functional Description 16.3.1.  Initialization 16.3.2.  Operation 16.3.2.1.  Event User Multiplexer Setup 16.3.2.2.  Event System Channel 16.3.2.3.  Event Generators 16.3.2.4.  Event Users 16.3.2.5.  Synchronization 16.3.2.6.  Software Event 16.3.3.  Sleep Mode Operation 16.3.4.  Debug Operation 16.4.  Register Summary 16.5.  Register Description 16.5.1.  Software Events 16.5.2.  Channel n Generator Selection 16.5.3.  User Channel MUX 17.  PORTMUX - Port Multiplexer 17.1.  Overview 17.2.  Register Summary 17.3.  Register Description 17.3.1.  EVSYS Pin Position 17.3.2.  CCL LUTn Pin Position 17.3.3.  USARTn Pin Position 17.3.4.  SPIn Pin Position 17.3.5.  TWIn Pin Position 17.3.6.  TCE0 Pin Position 17.3.7.  TCBn Pin Position 17.3.8.  TCFn Pin Position 18.  PORT - I/O Pin Configuration 18.1.  Features 18.2.  Overview 18.2.1.  Block Diagram 18.2.2.  Signal Description 18.3.  Functional Description 18.3.1.  Initialization 18.3.2.  Operation 18.3.2.1.  Basic Functions 18.3.2.2.  Port Configuration 18.3.2.3.  Pin Configuration 18.3.2.4.  Multi-Pin Configuration 18.3.2.5.  Virtual Ports 18.3.2.6.  Peripheral Override 18.3.3.  Interrupts 18.3.3.1.  Asynchronous Sensing Pin Properties 18.3.4.  Events 18.3.5.  Sleep Mode Operation 18.3.6.  Debug Operation 18.4.  Register Summary - PORTx 18.5.  Register Description - PORTx 18.5.1.  Data Direction 18.5.2.  Data Direction Set 18.5.3.  Data Direction Clear 18.5.4.  Data Direction Toggle 18.5.5.  Output Value 18.5.6.  Output Value Set 18.5.7.  Output Value Clear 18.5.8.  Output Value Toggle 18.5.9.  Input Value 18.5.10.  Interrupt Flags 18.5.11.  Port Control 18.5.12.  Multi-Pin Configuration 18.5.13.  Multi-Pin Control Update Mask 18.5.14.  Multi-Pin Control Set Mask 18.5.15.  Multi-Pin Control Clear Mask 18.5.16.  Pin n Control 18.5.17.  Event Generator Control A 18.6.  Register Summary - VPORTx 18.7.  Register Description - VPORTx 18.7.1.  Data Direction 18.7.2.  Output Value 18.7.3.  Input Value 18.7.4.  Interrupt Flags 19.  BOD - Brown-out Detector 19.1.  Features 19.2.  Overview 19.2.1.  Block Diagram 19.3.  Functional Description 19.3.1.  Initialization 19.3.2.  Interrupts 19.3.3.  Sleep Mode Operation 19.3.4.  Configuration Change Protection 19.4.  Register Summary 19.5.  Register Description 19.5.1.  Control A 19.5.2.  Control B 19.5.3.  VLM Control 19.5.4.  Interrupt Control 19.5.5.  VLM Interrupt Flags 19.5.6.  VLM Status 20.  VREF - Voltage Reference 20.1.  Features 20.2.  Overview 20.2.1.  Block Diagram 20.3.  Functional Description 20.3.1.  Initialization 20.4.  Register Summary 20.5.  Register Description 20.5.1.  Analog Comparator Reference 21.  WDT - Watchdog Timer 21.1.  Features 21.2.  Overview 21.2.1.  Block Diagram 21.3.  Functional Description 21.3.1.  Initialization 21.3.2.  Clocks 21.3.3.  Operation 21.3.3.1.  Normal Mode 21.3.3.2.  Window Mode 21.3.3.3.  Preventing Unintentional Changes 21.3.4.  Sleep Mode Operation 21.3.5.  Debug Operation 21.3.6.  Synchronization 21.3.7.  Configuration Change Protection 21.4.  Register Summary 21.5.  Register Description 21.5.1.  Control A 21.5.2.  Status 22.  TCB - 16-Bit Timer/Counter Type B 22.1.  Features 22.2.  Overview 22.2.1.  Block Diagram 22.2.2.  Signal Description 22.3.  Functional Description 22.3.1.  Definitions 22.3.2.  Initialization 22.3.3.  Operation 22.3.3.1.  Modes 22.3.3.1.1.  Periodic Interrupt Mode 22.3.3.1.2.  Time-Out Check Mode 22.3.3.1.3.  Input Capture on Event Mode 22.3.3.1.4.  Input Capture Frequency Measurement Mode 22.3.3.1.5.  Input Capture Pulse-Width Measurement Mode 22.3.3.1.6.  Input Capture Frequency and Pulse-Width Measurement Mode 22.3.3.1.7.  Single-Shot Mode 22.3.3.1.8.  8-bit PWM Mode 22.3.3.2.  Output 22.3.3.3.  32-Bit Input Capture 22.3.3.4.  Noise Canceler 22.3.3.5.  Synchronized with Timer/Counter Type E 22.3.3.6.  Port Override 22.3.4.  Events 22.3.5.  Interrupts 22.3.6.  Sleep Mode Operation 22.4.  Register Summary 22.5.  Register Description 22.5.1.  Control A 22.5.2.  Control B 22.5.3.  Control C 22.5.4.  Event Control 22.5.5.  Interrupt Control 22.5.6.  Interrupt Flags 22.5.7.  Status 22.5.8.  Debug Control 22.5.9.  Temporary Value 22.5.10.  Count 22.5.11.  Capture/Compare 23.  TCE - 16-Bit Timer/Counter Type E 23.1.  Features 23.2.  Overview 23.3.  Functional Description 23.3.1.  Definitions 23.3.2.  Initialization 23.3.3.  Clock Generation 23.3.4.  Operation 23.3.4.1.  Normal Operation 23.3.4.2.  Double Buffering 23.3.4.3.  Changing the Period 23.3.4.4.  Compare Channel 23.3.4.4.1.  Waveform Generation 23.3.4.4.2.  Frequency Waveform Generation (FRQ) 23.3.4.4.3.  Single-Slope PWM Generation 23.3.4.4.4.  Dual-Slope PWM 23.3.4.4.5.  Port Override for Waveform Generation 23.3.4.5.  Timer/Counter Commands 23.3.4.6.  High Resolution 23.3.4.7.  Amplitude, Offset and Fractional Compare Value 23.3.4.8.  Interfacing with Waveform Extension 23.3.5.  Events 23.3.6.  Interrupts 23.3.7.  Sleep Mode Operation 23.4.  Register Summary 23.5.  Register Description 23.5.1.  Control A 23.5.2.  Control B 23.5.3.  Control C 23.5.4.  Control D 23.5.5.  Control Register E Clear 23.5.6.  Control Register E Set 23.5.7.  Control Register F Clear 23.5.8.  Control Register F Set 23.5.9.  Event Generation Control 23.5.10.  Event Control 23.5.11.  Interrupt Control Register 23.5.12.  Interrupt Flag Register 23.5.13.  Debug Control Register 23.5.14.  Temporary Register 23.5.15.  Counter Register 23.5.16.  Amplitude Register 23.5.17.  Offset Register 23.5.18.  Period Register 23.5.19.  Compare n Register 23.5.20.  Period Buffer Register 23.5.21.  Compare n Buffer Register 24.  WEX - Waveform Extension for the 16-Bit Timer/Counter Type E 24.1.  Feature Description 24.2.  Overview 24.3.  Functional Description 24.3.1.  Initialization 24.3.2.  Operations 24.3.2.1.  Input Matrix 24.3.2.2.  Dead-Time Insertion 24.3.3.  Pattern Generation 24.3.4.  Port Override 24.3.5.  Faults 24.3.6.  Sleep Mode Operation 24.3.7.  Configuration Change Protection 24.4.  Register Summary 24.5.  Register Description 24.5.1.  Control A 24.5.2.  Control B 24.5.3.  Control C 24.5.4.  Event Control A 24.5.5.  Event Control B 24.5.6.  Event Control C 24.5.7.  Buffer Valid Control 24.5.8.  Blanking Control 24.5.9.  Blanking Time 24.5.10.  Fault Control 24.5.11.  Fault Drive 24.5.12.  Fault Output 24.5.13.  Interrupt Control 24.5.14.  Interrupt Flags 24.5.15.  Status 24.5.16.  Dead-Time Low Side 24.5.17.  Dead-Time High Side 24.5.18.  Dead-Time Both Sides 24.5.19.  DTI Swap 24.5.20.  Pattern Generation Mode Override 24.5.21.  Pattern Generation Mode Output 24.5.22.  Output Override Enable 24.5.23.  Dead-Time Low Side Buffer 24.5.24.  Dead-Time High Side Buffer 24.5.25.  Dead-Time Both Sides Buffer 24.5.26.  DTI Swap Buffer 24.5.27.  Pattern Generation Mode Override Buffer 24.5.28.  Pattern Generation Mode Output Buffer 25.  TCF - 24-bit Timer/Counter Type F 25.1.  Features 25.2.  Overview 25.2.1.  Block Diagram 25.2.2.  Signal Description 25.3.  Functional Description 25.3.1.  Definitions 25.3.2.  Initialization 25.3.3.  Operation 25.3.3.1.  Register Synchronization Categories 25.3.3.2.  Waveform Generation Modes 25.3.3.2.1.  Frequency Waveform Generation 25.3.3.2.2.  NCO Pulse-Frequency Waveform Generation 25.3.3.2.3.  NCO Fixed Duty-Cycle Frequency Waveform Generation 25.3.3.2.4.  8-Bit PWM Mode 25.3.3.3.  Output 25.3.3.4.  Noise Canceler 25.3.4.  Operation Considerations 25.3.5.  Events 25.3.6.  Interrupts 25.3.7.  Sleep Mode Operation 25.4.  Register Summary 25.5.  Register Description 25.5.1.  Control A 25.5.2.  Control B 25.5.3.  Control C 25.5.4.  Control D 25.5.5.  Event Control 25.5.6.  Interrupt Control 25.5.7.  Interrupt Flags 25.5.8.  Status 25.5.9.  Debug Control 25.5.10.  Counter Register 25.5.11.  Compare Register 26.  RTC - Real-Time Counter 26.1.  Features 26.2.  Overview 26.2.1.  RTC Block Diagram 26.3.  Clocks 26.4.  RTC Functional Description 26.4.1.  Initialization 26.4.1.1.  Configure the Clock CLK_RTC 26.4.1.2.  Configure RTC 26.4.2.  Operation - RTC 26.4.2.1.  Enabling and Disabling 26.5.  PIT Functional Description 26.5.1.  Initialization 26.5.2.  Operation - PIT 26.5.2.1.  Enabling and Disabling 26.5.2.2.  PIT Interrupt Timing 26.6.  Crystal Error Correction 26.7.  Events 26.8.  Interrupts 26.9.  Sleep Mode Operation 26.10.  Synchronization 26.11.  Debug Operation 26.12.  Register Summary 26.13.  Register Description 26.13.1.  Control A 26.13.2.  Status 26.13.3.  Interrupt Control 26.13.4.  Interrupt Flag 26.13.5.  Temporary 26.13.6.  Debug Control 26.13.7.  Crystal Frequency Calibration 26.13.8.  Clock Selection 26.13.9.  Count 26.13.10.  Period 26.13.11.  Compare 26.13.12.  Periodic Interrupt Timer Control A 26.13.13.  Periodic Interrupt Timer Status 26.13.14.  PIT Interrupt Control 26.13.15.  PIT Interrupt Flag 26.13.16.  Periodic Interrupt Timer Debug Control 26.13.17.  Periodic Timer Event Generation Control A 27.  USART - Universal Synchronous and Asynchronous Receiver and Transmitter 27.1.  Features 27.2.  Overview 27.2.1.  Block Diagram 27.2.2.  Signal Description 27.3.  Functional Description 27.3.1.  Initialization 27.3.2.  Operation 27.3.2.1.  Frame Formats 27.3.2.2.  Clock Generation 27.3.2.2.1.  The Fractional Baud Rate Generator 27.3.2.3.  Data Transmission 27.3.2.3.1.  Disabling the Transmitter 27.3.2.4.  Data Reception 27.3.2.4.1.  Receiver Error Flags 27.3.2.4.2.  Disabling the Receiver 27.3.2.4.3.  Flushing the Receive Buffer 27.3.3.  Communication Modes 27.3.3.1.  Synchronous Operation 27.3.3.1.1.  Clock Operation 27.3.3.1.2.  External Clock Limitations 27.3.3.1.3.  USART in Host SPI Mode 27.3.3.1.3.1.  Frame Formats 27.3.3.1.3.2.  Clock Generation 27.3.3.1.3.3.  Data Transmission 27.3.3.1.3.4.  Data Reception 27.3.3.1.3.5.  USART in Host SPI Mode vs. SPI 27.3.3.2.  Asynchronous Operation 27.3.3.2.1.  Clock Recovery 27.3.3.2.2.  Data Recovery 27.3.3.2.3.  Error Tolerance 27.3.3.2.4.  Double-Speed Operation 27.3.3.2.5.  Auto-Baud 27.3.3.2.6.  Half-Duplex Operation 27.3.3.2.6.1.  One-Wire Mode 27.3.3.2.6.2.  RS-485 Mode 27.3.3.2.7.  IRCOM Mode of Operation 27.3.4.  Additional Features 27.3.4.1.  Parity 27.3.4.2.  Start-of-Frame Detection 27.3.4.3.  Multiprocessor Communication 27.3.4.3.1.  Using Multiprocessor Communication 27.3.5.  Events 27.3.6.  Interrupts 27.4.  Register Summary 27.5.  Register Description 27.5.1.  Receiver Data Register Low Byte 27.5.2.  Receiver Data Register High Byte 27.5.3.  Transmit Data Register Low Byte 27.5.4.  Transmit Data Register High Byte 27.5.5.  USART Status Register 27.5.6.  Control A 27.5.7.  Control B 27.5.8.  Control C - Normal Mode 27.5.9.  Control C - Host SPI Mode 27.5.10.  Baud Register 27.5.11.  Control D 27.5.12.  Debug Control Register 27.5.13.  IrDA Control Register 27.5.14.  IRCOM Transmitter Pulse Length Control Register 27.5.15.  IRCOM Receiver Pulse Length Control Register 28.  SPI - Serial Peripheral Interface 28.1.  Features 28.2.  Overview 28.2.1.  Block Diagram 28.2.2.  Signal Description 28.3.  Functional Description 28.3.1.  Initialization 28.3.2.  Operation 28.3.2.1.  Host Mode Operation 28.3.2.1.1.  Normal Mode 28.3.2.1.2.  Buffer Mode 28.3.2.1.3.  SS Pin Functionality in Host Mode - Multi-Host Support 28.3.2.2.  Client Mode 28.3.2.2.1.  Normal Mode 28.3.2.2.2.  Buffer Mode 28.3.2.2.3.  SS Pin Functionality in Client Mode 28.3.2.3.  Data Modes 28.3.2.4.  Events 28.3.2.5.  Interrupts 28.4.  Register Summary 28.5.  Register Description 28.5.1.  Control A 28.5.2.  Control B 28.5.3.  Interrupt Control 28.5.4.  Interrupt Flags - Normal Mode 28.5.5.  Interrupt Flags - Buffer Mode 28.5.6.  Data 29.  TWI - Two-Wire Interface 29.1.  Features 29.2.  Overview 29.2.1.  Block Diagram 29.2.2.  Signal Description 29.3.  Functional Description 29.3.1.  General TWI Bus Concepts 29.3.2.  TWI Basic Operation 29.3.2.1.  Initialization 29.3.2.1.1.  Host Initialization 29.3.2.1.2.  Client Initialization 29.3.2.2.  TWI Host Operation 29.3.2.2.1.  Clock Generation 29.3.2.2.2.  TWI Bus State Logic 29.3.2.2.3.  Transmitting Address Packets 29.3.2.2.3.1.  Case M1: Address Packet Transmit Complete - Direction Bit Set to ‘0’ 29.3.2.2.3.2.  Case M2: Address Packet Transmit Complete - Direction Bit Set to ‘1’ 29.3.2.2.3.3.  Case M3: Address Packet Transmit Complete - Address not Acknowledged by Client 29.3.2.2.3.4.  Case M4: Arbitration Lost or Bus Error 29.3.2.2.4.  Transmitting Data Packets 29.3.2.2.5.  Receiving Data Packets 29.3.2.3.  TWI Client Operation 29.3.2.3.1.  Receiving Address Packets 29.3.2.3.1.1.  Case S1: Address Packet Accepted - Direction Bit Set to ‘0’ 29.3.2.3.1.2.  Case S2: Address Packet Accepted - Direction Bit Set to ‘1’ 29.3.2.3.1.3.  Case S3: Stop Condition Received 29.3.2.3.1.4.  Case S4: Collision 29.3.2.3.2.  Receiving Data Packets 29.3.2.3.3.  Transmitting Data Packets 29.3.3.  Additional Features 29.3.3.1.  SMBus 29.3.3.1.1.  Compliance to SMBus Specifications 29.3.3.2.  Multi-Host 29.3.3.3.  Smart Mode 29.3.3.4.  Dual Mode 29.3.3.5.  Quick Command Mode 29.3.3.6.  10-Bit Address 29.3.4.  Interrupts 29.3.5.  Sleep Mode Operation 29.3.6.  Debug Operation 29.4.  Register Summary 29.5.  Register Description 29.5.1.  Control A 29.5.2.  Dual Mode Control Configuration 29.5.3.  Debug Control 29.5.4.  Host Control A 29.5.5.  Host Control B 29.5.6.  Host Status 29.5.7.  Host Baud Rate 29.5.8.  Host Address 29.5.9.  Host Data 29.5.10.  Client Control A 29.5.11.  Client Control B 29.5.12.  Client Status 29.5.13.  Client Address 29.5.14.  Client Data 29.5.15.  Client Address Mask 30.  CRCSCAN - Cyclic Redundancy Check Memory Scan 30.1.  Features 30.2.  Overview 30.2.1.  Block Diagram 30.3.  Functional Description 30.3.1.  Initialization 30.3.2.  Operation 30.3.2.1.  Checksum 30.3.3.  Interrupts 30.3.4.  Sleep Mode Operation 30.3.5.  Debug Operation 30.4.  Register Summary 30.5.  Register Description 30.5.1.  Control A 30.5.2.  Control B 30.5.3.  Status 31.  CCL - Configurable Custom Logic 31.1.  Features 31.2.  Overview 31.2.1.  Block Diagram 31.2.2.  Signal Description 31.2.2.1.  CCL Input Selection MUX 31.3.  Functional Description 31.3.1.  Operation 31.3.1.1.  Enable-Protected Configuration 31.3.1.2.  Enabling, Disabling, and Resetting 31.3.1.3.  Truth Table Logic 31.3.1.4.  Truth Table Inputs Selection 31.3.1.5.  Filter 31.3.1.6.  Edge Detector 31.3.1.7.  Sequencer Logic 31.3.1.8.  Clock Source Settings 31.3.2.  Interrupts 31.3.3.  Events 31.3.4.  Sleep Mode Operation 31.4.  Register Summary 31.5.  Register Description 31.5.1.  Control A 31.5.2.  Sequencer Control 0 31.5.3.  Sequencer Control 1 31.5.4.  Interrupt Control 0 31.5.5.  Interrupt Flag 31.5.6.  LUT n Control A 31.5.7.  LUT n Control B 31.5.8.  LUT n Control C 31.5.9.  TRUTHn 32.  AC - Analog Comparator 32.1.  Features 32.2.  Overview 32.2.1.  Block Diagram 32.2.2.  Signal Description 32.3.  Functional Description 32.3.1.  Initialization 32.3.2.  Operation 32.3.2.1.  Input Hysteresis 32.3.2.2.  Input and Reference Selection 32.3.2.3.  Normal Mode 32.3.2.4.  Power Modes 32.3.2.5.  Window Mode 32.3.3.  Events 32.3.4.  Interrupts 32.3.5.  Sleep Mode Operation 32.4.  Register Summary 32.5.  Register Description 32.5.1.  Control A 32.5.2.  Control B 32.5.3.  MUX Control 32.5.4.  DAC Voltage Reference 32.5.5.  Interrupt Control 32.5.6.  Status 33.  ADC - Analog-to-Digital Converter 33.1.  Features 33.2.  Overview 33.2.1.  Block Diagram 33.2.2.  Signal Description 33.3.  Functional Description 33.3.1.  Definitions 33.3.2.  Basic Operation 33.3.3.  Operation 33.3.3.1.  Operation Modes 33.3.3.2.  Conversion Triggers 33.3.3.3.  Output Formats 33.3.3.4.  ADC Clock 33.3.3.5.  Input and Reference Selection 33.3.3.5.1.  Programmable Gain Amplifier 33.3.3.5.2.  Offset Reduction by Sign Chopping 33.3.3.5.3.  Analog Input Circuit 33.3.3.6.  Conversion Timing 33.3.3.6.1.  Single Conversion 33.3.3.6.2.  Series Accumulation 33.3.3.6.3.  Burst Accumulation 33.3.3.6.4.  Single Conversion Mode with PGA 33.3.3.6.5.  Series Accumulation with PGA 33.3.3.6.6.  Burst Accumulation with PGA 33.3.3.7.  Temperature Measurement 33.3.3.8.  Window Comparator 33.3.4.  Events 33.3.5.  Interrupts 33.3.6.  Sleep Mode Operation 33.3.7.  Debug Operation 33.4.  Register Summary 33.5.  Register Description 33.5.1.  Control A 33.5.2.  Control B 33.5.3.  Control C 33.5.4.  Control D 33.5.5.  Interrupt Control 33.5.6.  Interrupt Flags 33.5.7.  Status 33.5.8.  Debug Control 33.5.9.  Control E 33.5.10.  Control F 33.5.11.  Command 33.5.12.  PGA Control 33.5.13.  Positive Input Multiplexer 33.5.14.  Negative Input Multiplexer 33.5.15.  Result 33.5.16.  Sample 33.5.17.  Temporary n 33.5.18.  Window Comparator Low Threshold 33.5.19.  Window Comparator High Threshold 34.  UPDI - Unified Program and Debug Interface 34.1.  Features 34.2.  Overview 34.2.1.  Block Diagram 34.2.2.  Addressing the Program Memory Space 34.2.3.  Clocks 34.2.4.  Physical Layer 34.2.5.  I/O Lines and Connections 34.3.  Functional Description 34.3.1.  Principle of Operation 34.3.1.1.  UPDI UART 34.3.1.2.  BREAK Character 34.3.1.2.1.  BREAK in One-Wire Mode 34.3.1.3.  SYNCH Character 34.3.1.3.1.  SYNCH in One-Wire Mode 34.3.2.  Operation 34.3.2.1.  UPDI Enabling 34.3.2.1.1.  One-Wire Enable 34.3.2.1.2.  UPDI Enable with High-Voltage Override of UPDI Pin 34.3.2.2.  UPDI Disabling 34.3.2.2.1.  Disable During Start-Up 34.3.2.2.1.1.  Time-Out Disable 34.3.2.2.1.2.  Incorrect SYNCH Pattern 34.3.2.2.2.  UPDI Regular Disable 34.3.2.3.  UPDI Communication Error Handling 34.3.2.4.  Direction Change 34.3.3.  UPDI Instruction Set 34.3.3.1.  LDS - Load Data from Data Space Using Direct Addressing 34.3.3.2.  STS - Store Data to Data Space Using Direct Addressing 34.3.3.3.  LD - Load Data from Data Space Using Indirect Addressing 34.3.3.4.  ST - Store Data from UPDI to Data Space Using Indirect Addressing 34.3.3.5.  LDCS - Load Data from Control and Status Register Space 34.3.3.6.  STCS - Store Data to Control and Status Register Space 34.3.3.7.  REPEAT - Set Instruction Repeat Counter 34.3.3.8.  KEY - Set Activation Key or Send System Information Block 34.3.4.  CRC Checking of Flash During Boot 34.3.5.  System Clock Measurement with UPDI 34.3.6.  Inter-Byte Delay 34.3.7.  System Information Block 34.3.8.  Enabling of Key Protected Interfaces 34.3.8.1.  Chip Erase 34.3.8.2.  NVM Programming 34.3.8.3.  User Row Programming 34.3.9.  Events 34.3.10.  Sleep Mode Operation 34.4.  Register Summary 34.5.  Register Description 34.5.1.  Status A 34.5.2.  Status B 34.5.3.  Control A 34.5.4.  Control B 34.5.5.  ASI Key Status 34.5.6.  ASI Reset Request 34.5.7.  ASI Control A 34.5.8.  ASI System Control A 34.5.9.  ASI System Status 34.5.10.  ASI CRC Status 35.  Instruction Set Summary 36.  Electrical Characteristics 36.1.  Disclaimer 36.2.  Absolute Maximum Ratings 36.3.  Standard Operating Conditions 36.4.  Supply Voltage 36.5.  Power Consumption 36.6.  Peripherals Power Consumption 36.7.  I/O Pins 36.8.  Memory Programming Specifications 36.9.  Thermal Specifications 36.10.  CLKCTRL 36.10.1.  Internal Oscillators 36.10.2.  PLL 36.10.3.  XOSC32K 36.10.4.  External Clock 36.10.5.  System Clock 36.11.  RSTCTRL and BOD 36.12.  VREF 36.13.  USART 36.14.  SPI 36.15.  TWI 36.16.  ADC 36.17.  AC 36.18.  UPDI 37.  Characteristics Graphs 38.  Ordering Information 39.  Packaging Information 39.1.  Online Package Drawings 39.2.  Package Marking Information 39.2.1.  14-Pin SOIC 39.2.2.  14-Pin TSSOP 39.2.3.  20-Pin SSOP 39.2.4.  28-Pin SPDIP 39.2.5.  28-Pin SSOP 39.2.6.  28-Pin VQFN 39.2.7.  32-Pin VQFN 39.2.8.  32-Pin VQFN Wettable Flanks 39.2.9.  32-Pin TQFP 39.3.  Package Drawings 39.3.1.  14-Pin SOIC 39.3.2.  14-Pin TSSOP 39.3.3.  20-Pin SSOP 39.3.4.  28-Pin SPDIP 39.3.5.  28-Pin SSOP 39.3.6.  28-Pin VQFN 39.3.7.  32-Pin VQFN 39.3.8.  32-Pin TQFP 40.  Data Sheet Revision History 40.1.  Revision History Microchip Information Trademarks Legal Notice Microchip Devices Code Protection Feature