Datasheet EPC23108 (Efficient Power Conversion) - 7
| 制造商 | Efficient Power Conversion |
| 描述 | 100V, 35 A ePower Stage IC |
| 页数 / 页 | 17 / 7 — eGaN® IC DATASHEET. Typical Output Charge and COSS Stored Energy. Figure … |
| 文件格式/大小 | PDF / 1.9 Mb |
| 文件语言 | 英语 |
eGaN® IC DATASHEET. Typical Output Charge and COSS Stored Energy. Figure 5a: QOSS and EOSS of High-Side Power GaN FET
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eGaN® IC DATASHEET
EPC23109
Typical Output Charge and COSS Stored Energy Figure 5a: QOSS and EOSS of High-Side Power GaN FET Figure 5b: QOSS and EOSS of Low-Side Power GaN FET
60 2.5 60 2.5 48 2.0 48 2.0
) ) gy (μJ) gy (μJ) ge (nC ge (nC
36
har
1.5 36
har
1.5
ed Ener ed Ener utput C Stor Stor
24 1.0
utput C
24 1.0
OSS OSS − O − C − O − C QOSS QOSS
12
E OSS
0.5 12
E OSS
0.5 0 0.0 0 0.0 0 25 50 75 100 0 25 50 75 100
VDS − Drain-to-Source Voltage (V) VDS − Drain-to-Source Voltage (V) Power GaN FETs Typical RDS(on) vs. Temperature Figure 6a: High Side FET Normalized RDS(on) Figure 6b: Low Side FET Normalized RDS(on)
1.8 1.8 1.6 1.6 1.4 1.4
(mΩ) (mΩ)
1.2 1.2 1.0
R DS(on)_HS R DS(on)_HS
1.0 0.8 0.8 0.6 0.6 -50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
Temperature (°C) Temperature (°C) Truth Table SD/STB(1) VDD VBOOT – VPHASE EN(2) PWM HS FET LS FET
Low – – – – OFF OFF <VDD_POR – – – OFF OFF 0 – OFF OFF >VDD_POR <VBOOT_POR 1 0 OFF ON High 1 1 OFF OFF 0 – OFF OFF >VDD_POR >VBOOT_POR 1 0 OFF ON 1 1 ON OFF (1) (SD/STB) immediately inhibits PWM inputs when pul ed low. If VDD and VDRV are not directly connected, the IC enters in standby mode (low quiescent current). (2) EN immediately inhibits PWM inputs when pul ed low. EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2026 | For more information: info@epc-co.com | 7
EPC23109
Typical Output Charge and COSS Stored Energy Figure 5a: QOSS and EOSS of High-Side Power GaN FET Figure 5b: QOSS and EOSS of Low-Side Power GaN FET
60 2.5 60 2.5 48 2.0 48 2.0
) ) gy (μJ) gy (μJ) ge (nC ge (nC
36
har
1.5 36
har
1.5
ed Ener ed Ener utput C Stor Stor
24 1.0
utput C
24 1.0
OSS OSS − O − C − O − C QOSS QOSS
12
E OSS
0.5 12
E OSS
0.5 0 0.0 0 0.0 0 25 50 75 100 0 25 50 75 100
VDS − Drain-to-Source Voltage (V) VDS − Drain-to-Source Voltage (V) Power GaN FETs Typical RDS(on) vs. Temperature Figure 6a: High Side FET Normalized RDS(on) Figure 6b: Low Side FET Normalized RDS(on)
1.8 1.8 1.6 1.6 1.4 1.4
(mΩ) (mΩ)
1.2 1.2 1.0
R DS(on)_HS R DS(on)_HS
1.0 0.8 0.8 0.6 0.6 -50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
Temperature (°C) Temperature (°C) Truth Table SD/STB(1) VDD VBOOT – VPHASE EN(2) PWM HS FET LS FET
Low – – – – OFF OFF <VDD_POR – – – OFF OFF 0 – OFF OFF >VDD_POR <VBOOT_POR 1 0 OFF ON High 1 1 OFF OFF 0 – OFF OFF >VDD_POR >VBOOT_POR 1 0 OFF ON 1 1 ON OFF (1) (SD/STB) immediately inhibits PWM inputs when pul ed low. If VDD and VDRV are not directly connected, the IC enters in standby mode (low quiescent current). (2) EN immediately inhibits PWM inputs when pul ed low. EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2026 | For more information: info@epc-co.com | 7