Datasheet EPC23108 (Efficient Power Conversion) - 5

eGaN® IC DATASHEET
EPC23109
Electrical Characteristics
(continued)
Electrical Characteristics# (continued) SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Power FETs Quiescent Currents – include internal biasing circuits(3)
IQ_VIN-SW Quiescent current (VIN to SW) PWM = 0 V, SD/STB /EN = 5 V, VIN = 100 V, SW = 0 V 230 µA IQ_SW-PGND Quiescent current (SW to PGND) PWM = 0 V, SD/STB /EN = 5 V, VIN = 100 V, SW = 100 V 3.4 mA PWM = 0 V, SD/STB /EN = 5 V, V I IN = 100 V 165 230 Q_VIN-PGND Quiescent current (VIN to PGND) µA PWM = 0 V, SD/STB /EN = 5 V, VIN = 48 V 160
Dynamic Characteristics (Logic Input to Output Switching Node SW)
(See Figure 3 for Timing Diagram) PW_min Minimum pulse width 50% to 50% width (5) 45 (1) tFilter Input filter cutoff time 50% to 50% width, PWM and EN 15 tShutdown Shutdown propagation delay 50% to 50% width, HS and LS FET turn-OFF 41 (1) t_delayEN_on EN ON propagation delay 50% to 50% width, HS and LS FET turn-ON (EN = 5 V) 42 t_delayHS_on High-side OFF propagation delay SW = 0 V and HS FET turn-ON 60 t_delayLS_off Low-side ON propagation delay SW = 48 V and HS FET turn-ON 60 t_delayHS_on High-side OFF propagation delay SW = 48 V and LS FET turn-OFF 36 t_delay ns LS_off Low-side ON propagation delay SW = 0 V and HS FET turn-OFF 36 t_matchon Delay matching LSoff to HSon LS turn-ON minus HS turn-ON 3.5 t_matchoff Delay matching HSoff to LSon LS turn-OFF to HS turn-OFF -3 t_deadtime Cross-conduction lockout embedded dead time LS turn-OFF to HS turn-ON or HS turn-OFF to LS turn-ON - embedded dead time 24 t_rise SW rise time at high-side FET turn-ON HS turn-ON current exiting from SW node, 0 V to 48 V, SW_HS10 (motor drive, hard switching) RBOOT = 10 Ω, ILOAD = 5 A(4) 5 t_fall SW fall time at low-side FET turn-ON LS turn-ON current entering the SW node, 48 V to 0 V, SW_LS10 (motor drive, hard switching) RDRV = 10 Ω, ILOAD = 5 A(4) 5 (1) Not tested, guaranteed by design (2) ISW is positive when exiting from SW node (3) The quiescent currents include the power FET IDSS as well as the internal circuits biasing currents (4) Measured on application board EPC91129 (5) There is no max limit for the pulse width length in time, as long as the voltage supply is not below the power on reset threshold limit. PW_max for the high- side FET depends also on the external bootstrap capacitance value. If the CBOOT voltage fal s below power on reset threshold voltage, the high-side GaN FET is switched OFF. The high-side circuit can be biased from an external 5 V floating voltage supply to al ow infinite turn on of the high-side FET. EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2026 | For more information: info@epc-co.com | 5