Datasheet UCC34141-Q1 (Texas Instruments) - 7

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UCC34141-Q1 www.ti.com
SLUSFP1D – APRIL 2024 – REVISED APRIL 2026
6.4 Thermal Information DHA (SOIC) THERMAL METRIC
(1)
UNIT 16 PINS
RθJA Junction-to-ambient thermal resistance 63.2 °C/W RθJC(top) Junction-to-case (top) thermal resistance 32.3 °C/W RθJB Junction-to-board thermal resistance 20.1 °C/W ΨJA Junction-to-ambient characterization parameter 47.8 °C/W ΨJB Junction-to-board characterization parameter 20.5 °C/W ΨJT Junction-to-top characterization parameter 3 °C/W (1) The thermal resistances (R) are based on JEDEC board, and the characterization parameters (Ψ) are based on the EVM described in the Layout section. For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application note.
6.5 Insulation Specifications PARAMETER TEST CONDITIONS VALUE UNIT General
CLR External clearance (1) Shortest terminal-to-terminal distance through air > 8.2 mm CPG External creepage (1) Shortest terminal-to-terminal distance across the > 8.2 mm package surface Minimum internal gap (internal clearance – DTI Distance through the insulation > 70 µm transformer power isolation) CTI Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112 > 600 V Material group According to IEC 60664-1 I Rated mains voltage ≤ 300VRMS I-IV Overvoltage category Rated mains voltage ≤ 600VRMS I-IV Rated mains voltage ≤ 1000VRMS I-III
DIN EN IEC 60747-17 (VDE 0884-17) (Planned Certification Targets)
(2) VIORM Maximum repetitive peak isolation voltage AC voltage (bipolar) 1700 VPK AC voltage (sine wave) Time dependent dielectric 1202 VRMS V breakdown (TDDB) test IOWM Maximum working isolation voltage DC voltage 1700 VDC V V TEST = VIOTM, t = 60s (qualification); VTEST = 1.2 IOTM Maximum transient isolation voltage 7071 V × V PK IOTM, t = 1s (100% production) VIMP Maximum impulse voltage (3) Tested in air, 1.2/50μs waveform per IEC 62368-1 8000 VPK VIOSM Maximum surge isolation voltage (3) VIOSM ≥ 1.3 × VIMP; Tested in oil (qualification 10400 V test), 1.2/50µs waveform per IEC 62368-1 PK Method a: After I/O safety test subgroup 2/3, Vini ≤ 5 pC = VIOTM, tini = 60s; Vpd(m) = 1.2 × VIORM, tm = 10s Method a: After environmental tests subgroup 1, V ≤ 5 pC q ini = VIOTM, tini = 60s; Vpd(m) = 1.6 × VIORM, tm = pd Apparent charge (4) 10s Method b1: At routine test (100% production), Vini = 1.2 × VIOTM, tini = 1s; Vpd(m) = 1.875 × VIORM, tm ≤ 5 pC = 1s CIO Barrier capacitance, input to output (5) VIO = 0.4 sin (2πft), f = 1MHz < 3 pF VIO = 500V, TA = 25°C > 1012 Ω RIO Isolation resistance, input to output (5) VIO = 500V, 100°C ≤ TA ≤ 125°C > 1011 Ω VIO = 500V at TS = 150°C > 109 Ω Pollution degree 2 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: UCC34141-Q1 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Device Comparison 5 Pin Configuration and Functions 6 Specifications 6.1 Absolute Maximum Ratings 6.2 ESD Ratings 6.3 Recommended Operating Conditions 6.4 Thermal Information 6.5 Insulation Specifications 6.6 Electrical Characteristics 6.7 Safety Limiting Values 6.8 Typical Characteristics 7 Detailed Description 7.1 Overview 7.2 Functional Block Diagram 7.3 Feature Description 7.3.1 Power Stage Operation 7.3.1.1 VDD-COM Voltage Regulation 7.3.1.2 COM-VEE Voltage Regulation 7.3.1.3 COM-VEE Output Capability 7.3.2 Output Voltage Soft Start 7.3.3 ENA and Power-Good 7.3.4 Protection Functions 7.3.4.1 Input Undervoltage Lockout 7.3.4.2 Input Overvoltage Lockout 7.3.4.3 Output Undervoltage Protection 7.3.4.4 Output Overvoltage Protection 7.3.4.5 Output Short Circuit Protection 7.3.4.6 Over-Temperature Protection 7.3.4.7 BSW Pin Faults Protection 7.4 Device Functional Modes 8 Application and Implementation 8.1 Application Information 8.2 Typical Application 8.2.1 Design Requirements 8.2.2 Detailed Design Procedure 8.2.2.1 VDD-COM Voltage Regulation 8.2.2.2 COM-VEE Voltage Regulation and Single Output Configuration 8.3 System Examples 8.4 Power Supply Recommendations 8.5 Layout 8.5.1 Layout Guidelines 8.5.2 Layout Example 9 Device and Documentation Support 9.1 Third-Party Products Disclaimer 9.2 Documentation Support 9.2.1 Related Documentation 9.3 Receiving Notification of Documentation Updates 9.4 Support Resources 9.5 Trademarks 9.6 Electrostatic Discharge Caution 9.7 Glossary 10 Revision History 11 Mechanical, Packaging, and Orderable Information