Data SheetLTC7893PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS+VABSEVUVSETCCRRTTRUNDDDDSEN282726252423PLLIN/SPREAD 122 SENSE–MODE 221 VFBFREQ 320 ITHSS 419 ILIMLTC7893TEST 5TOP VIEW18 PGOOD(Not to scale)VPRG 617 TGUP29V7BIAS16 TGDNGNDDRV8CC15 SW91011121314PNCCCCCCSTVVVUDTGGOSTNBBOBEXTIBNOTES 1. EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB. 003 Figure 3. Pin ConfigurationTable 3. Pin DescriptionsPINNAMEDESCRIPTION External Synchronization Input to Phase Detector/Spread Spectrum Enable. When an external clock is applied to PLLIN/SPREAD, the phase-locked loop forces the rising BGx PLLIN/ 1 signal to synchronize with the rising edge of the external clock. When not SPREAD synchronizing to an external clock, tie this input to INTVCC to enable spread spectrum dithering of the oscillator, or to GND to disable spread spectrum dithering. Mode Select Input. This input determines how the LTC7893 operates at light loads. Connect MODE to GND to select the Burst Mode® operation. An internal 100kΩ resistor 2 MODE to GND also invokes Burst Mode operation when MODE is floating. Connect MODE to INTVCC to force continuous inductor current operation. Tying MODE to INTVCC through a 100kΩ resistor selects the pulse-skipping operation. Frequency Control Pin for the Internal Voltage Controlled Oscillator (VCO). Connect FREQ to GND for a fixed frequency of 370kHz. Connect FREQ to INTV 3 FREQ CC for a fixed frequency of 2.25MHz. Program frequencies between 100kHz and 3MHz by using a resistor between FREQ and GND. Minimize the capacitance on FREQ. External Soft Start Input. SS regulates the VFB voltage to the lesser of 1.2V or the 4 SS voltage on the SS pin. An internal 12μA pull-up current source is connected to SS. A capacitor to GND at SS sets the ramp time to the final regulated output voltage. The ramp time is equal to 1ms for every 10nF of capacitance. 5 TEST Test Pin. This pin must be soldered to PCB GND. Output Voltage Control Pin. This pin sets the adjustable output mode using the 6 VPRG external feedback resistors or the fixed 28V or 24V output mode. Floating VPRG programs the output from 1.2V to 100V with an external resistor divider, regulating VFB analog.com Rev. 0 9 of 48 Document Outline Features Applications General Description Typical Application TABLE OF CONTENTS Revision History Specifications Absolute Maximum Ratings Pin Configurations and Function Descriptions Typical Performance Characteristics Functional diagram Theory of Operation Main Control Loop Power and Bias Supplies (VBIAS, EXTVCC, DRVCC, and INTVCC) High-Side Bootstrap Capacitor Dead Time Control (DTCA and DTCB Pins) Startup and Shutdown (RUN and SS Pins) Light Load Operation: Burst Mode Operation, Pulse-Skipping, or Forced Continuous Mode (MODE Pin) Frequency Selection, Spread Spectrum, and Phase-Locked Loop (FREQ and PLLIN/SPREAD Pins) Output Overvoltage Protection Power Good Applications Information Inductor Value Calculation Inductor Core Selection Current Sense Selection Low Value Resistor Current Sensing Inductor DCR Current Sensing Setting the Operating Frequency Selecting the Light-Load Operating Mode Dead Time Control (DTCA and DTCB Pins) DTCx Pin Tied to Ground (Adaptive Dead Time Control) DTCx Pin connected with a resistor to GND Power FET Selection CIN and COUT Selection Setting the Output Voltage RUN Pin and Undervoltage Lockout Soft-Start (SS Pin) INTVCC Regulators (OPTI-DRIVE) Topside FET Driver Supply (CB) Minimum On-Time Considerations Fault Conditions: Overtemperature Protection Phase-Locked Loop and Frequency Synchronization Efficiency Considerations Checking Transient Response Design Example PCB Board Layout Checklist PCB Layout Debugging Typical Applications Related Parts Outline Dimensions Ordering Guide