Datasheet A4988 (Allegro) - 10

DMOS Microstepping Driver A4988 with Translator and Overcurrent Protection VREG (VREG).
This internally generated voltage is used to operate the sink-side FET outputs. The nominal output voltage of the VREG 5 A / div. Fault terminal is 7 V. The VREG pin must be decoupled with a 0.22 µF ceramic capacitor to ground. V latched REG is internally monitored. In the case of a fault condition, the FET outputs of the A4988 are disabled. Capacitor values should be Class 2 dielectric ±15% maximum, or tolerance R, according to EIA (Electronic Industries Alliance) specifications.
Enable Input (
¯E ¯N¯ ¯A ¯B ¯L ¯E
).
This input turns on or off all of the FET outputs. When set to a logic high, the outputs are disabled. When set to a logic low, the internal control enables the outputs as required. The translator inputs STEP, DIR, and MSx, as well as t → the internal sequencing logic, all remain active, independent of the Figure 4: Short-to-Ground Event ¯E ¯N ¯A ¯B ¯L ¯E input state.
Shutdown.
In the event of a fault, overtemperature (excess TJ) or an undervoltage (on VCP), the FET outputs of the A4988 are disabled until the fault condition is removed. At power-on, the UVLO (undervoltage lockout) circuit disables the FET outputs 5 A / div. and resets the translator to the Home state. Fixed off-time
Sleep Mode

(
¯S ¯L ¯E ¯E ¯P
).
To minimize power consumption when the motor is not in use, this input disables much of the internal circuitry including the output FETs, current regulator, and charge pump. A logic low on the S¯ ¯L ¯E ¯E ¯P pin puts the A4988 into Sleep mode. A logic high allows normal operation, as well as startup (at which time the A4988 drives the motor to the Home microstep position). When emerging from Sleep mode, in order to allow the charge pump to stabilize, provide a delay of 1 ms t → before issuing a Step command. Figure 5. Shorted Load (OUTxA → OUTxB) in Slow Decay Mode
Mixed Decay Operation.
The bridge operates in Mixed decay mode, depending on the step sequence, as shown in Fig- ures 9 through 13. As the trip point is reached, the A4988 initially goes into a fast decay interval for 31.25% of the off-time, tOFF. After that, it switches to slow decay for the remainder of t 5 A / div. OFF. A timing diagram for this feature appears in Figure 7. Fixed off-time
Synchronous Rectification.
When a PWM-off cycle is triggered by an internal fixed-off time cycle, load current recircu- lates according to the decay mode selected by the control logic. This synchronous rectification feature turns on the appropriate FETs during current decay, and effectively shorts out the body diodes with the low FET R Fast decay portion ds(on). This reduces power dissipation significantly, and can eliminate the need for external Schottky (direction change) diodes in many applications. Synchronous rectification turns off t → when the load current approaches zero (0 A), preventing reversal of the load current. Figure 6: Shorted Load (OUTxA → OUTxB) in Mixed Decay Mode 10 Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com