Datasheet MP2315 (Monolithic Power Systems) - 10

MP2315 – 24V, 3A SYNC STEP DOWN CONVERTER OPERATION
The MP2315 is a high frequency synchronous Under the light load condition, the value of rectified step-down switch mode converter with VCOMP is low. When VCOMP is less than VAAM and built in internal power MOSFETs. It offers a VFB is less than VREF, VCOMP ramps up until it very compact solution to achieve 3A continuous exceeds VAAM. During this time, the internal output current over a wide input supply range clock is blocked, thus the MP2315 skips some with excellent load and line regulation. pulses for PFM (Pulse Frequency Modulation) The MP2315 operates in a fixed frequency, mode and achieves the light load power save. peak current control mode to regulate the Clock output voltage. A PWM cycle is initiated by the 1.1pF VOUT internal clock. The integrated high-side power HS_driver VAAM Q S 50pF 400k MOSFET is turned on and remains on until its R1 20k current reaches the value set by the COMP VCOMP VFB R voltage. When the power switch is off, it R2 VREF remains off until the next clock cycle starts. If, in VIL sense 95% of one PWM period, the current in the
Figure 2: Simplified AAM Control Logic
power MOSFET does not reach the COMP set current value, the power MOSFET will be
Enable/SYNC control
forced to turn off. EN is a digital control pin that turns the regulator on and off. Drive EN high to turn on
Internal Regulator
the regulator, drive it low to turn it off. There is Most of the internal circuitries are powered from an internal 1MEG resistor from EN to GND thus the 5V internal regulator. This regulator takes EN can be floated to shut down the chip. Also the VIN input and operates in the full VIN range. EN pin voltage was clamped to around 6.5V by When VIN is greater than 5.0V, the output of an internal zener-diode. Please use large the regulator is in full regulation. When VIN is enough pull up resistor connecting between VIN MP2393 lower than 5.0V, the output decreases, a 0.1uF and EN to limit the EN input current which ceramic capacitor for decoupling purpose is should be less than 100uA. Generally, around required. 100k resistor should be large enough for all the O
Error Amplifier
applications. The error amplifier compares the FB pin voltage The chip can be synchronized to external clock with the internal 0.8V reference (REF) and range from 200kHz up to 2MHz through this pin outputs a COMP voltage, which is used to 2ms right after output voltage is set, with the RECOMMENDED FOR control the power MOSFET current. The internal clock rising edge synchronized to the optimized internal compensation network external clock rising edge. EN synchronize logic NEW DESIGNS minimizes the external component counts and high voltage should higher than 2V. EN simplifies the control loop design. synchronize logic low voltage should lower than
AAM Operation
400mV. EN logic high pulse width must less The MP2315 has AAM (Advanced than 1.6µs. Otherwise the internal clock may NOT Asynchronous Modulation) power-save mode come and turn on high side MOSFET again. EN for light load. Connect a resistor from AAM pin logic low pulse width must less than 6µs, REFER T to GND to set AAM voltage. Under the heavy otherwise MP2315 may EN shutdown. load condition, the VCOMP is higher than VAAM.
Under-Voltage Lockout (UVLO)
When the clock goes high, the high-side power Under-voltage lockout (UVLO) is implemented MOSFET turns on and remains on until VILsense to protect the chip from operating at insufficient reaches the value set by the COMP voltage. supply voltage. The MP2315 UVLO comparator The internal clock resets every time when VCOMP monitors the output voltage of the internal is higher than VAAM. regulator, VCC. The UVLO rising threshold is MP2315 Rev. 1.01 www.MonolithicPower.com 10 1/8/2014 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved.