Datasheet MAX7219, MAX7221 (Analog Devices) - 6
| 制造商 | Analog Devices |
| 描述 | Serially Interfaced, 8-Digit, LED Display Drivers |
| 页数 / 页 | 15 / 6 — Table 1. Serial-Data Format (16 Bits). Detailed Description. Digit and … |
| 文件格式/大小 | PDF / 1.4 Mb |
| 文件语言 | 英语 |
Table 1. Serial-Data Format (16 Bits). Detailed Description. Digit and Control Registers. MAX7219/MAX7221 Differences
该数据表的模型线
文件文字版本
MAX7219/MAX7221 Serially Interfaced, 8-Digit LED Display Drivers CS tCSW OR LOAD t t CSH t CL tCH CSS tCP tLDCK CLK tDH tDS DIN D15 D14 D1 D0 tDO DOUT Figure 1. Timing Diagram
Table 1. Serial-Data Format (16 Bits)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X ADDRESS MSB DATA LSB
Detailed Description Digit and Control Registers MAX7219/MAX7221 Differences
Table 2 lists the 14 addressable digit and control registers. The digit registers are realized with an on-chip, 8x8 The MAX7219 and MAX7221 are identical except for two dual-port SRAM. They are addressed directly so that parameters: the MAX7221 segment drivers are slew-rate individual digits can be updated and retain data as long limited to reduce electromagnetic interference (EMI), and as V+ typically exceeds 2V. The control registers consist its serial interface is fully SPI compatible. of decode mode, display intensity, scan limit (number of
Serial-Addressing Modes
scanned digits), shutdown, and display test (all LEDs on). For the MAX7219, serial data at DIN, sent in 16-bit packets,
Shutdown Mode
is shifted into the internal 16-bit shift register with each When the MAX7219 is in shutdown mode, the scan oscillator is rising edge of CLK regardless of the state of LOAD. For halted, all segment current sources are pulled to ground, the MAX7221, CS must be low to clock data in or out. and all digit drivers are pulled to V+, thereby blanking the The data is then latched into either the digit or control registers display. The MAX7221 is identical, except the drivers are on the rising edge of LOAD/CS. LOAD/CS must go high high-impedance. Data in the digit and control registers concurrently with or after the 16th rising clock edge, but remains unaltered. Shutdown can be used to save power before the next rising clock edge or data will be lost. or as an alarm to flash the display by successively entering Data at DIN is propagated through the shift register and and leaving shutdown mode. For minimum supply current appears at DOUT 16.5 clock cycles later. Data is clocked in shutdown mode, logic inputs should be at ground or V+ out on the falling edge of CLK. Data bits are labeled (CMOS-logic levels). D0–D15 (Table 1). D8–D11 contain the register address. D0–D7 contain the data, and D12–D15 are “don’t care” Typically, it takes less than 250μs for the MAX7219/ bits. The first received is D15, the most significant bit MAX7221 to leave shutdown mode. The display driver can (MSB). be programmed while in shutdown mode, and shutdown mode can be overridden by the display-test function. www.maximintegrated.com Maxim Integrated │ 6
Table 1. Serial-Data Format (16 Bits)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X ADDRESS MSB DATA LSB
Detailed Description Digit and Control Registers MAX7219/MAX7221 Differences
Table 2 lists the 14 addressable digit and control registers. The digit registers are realized with an on-chip, 8x8 The MAX7219 and MAX7221 are identical except for two dual-port SRAM. They are addressed directly so that parameters: the MAX7221 segment drivers are slew-rate individual digits can be updated and retain data as long limited to reduce electromagnetic interference (EMI), and as V+ typically exceeds 2V. The control registers consist its serial interface is fully SPI compatible. of decode mode, display intensity, scan limit (number of
Serial-Addressing Modes
scanned digits), shutdown, and display test (all LEDs on). For the MAX7219, serial data at DIN, sent in 16-bit packets,
Shutdown Mode
is shifted into the internal 16-bit shift register with each When the MAX7219 is in shutdown mode, the scan oscillator is rising edge of CLK regardless of the state of LOAD. For halted, all segment current sources are pulled to ground, the MAX7221, CS must be low to clock data in or out. and all digit drivers are pulled to V+, thereby blanking the The data is then latched into either the digit or control registers display. The MAX7221 is identical, except the drivers are on the rising edge of LOAD/CS. LOAD/CS must go high high-impedance. Data in the digit and control registers concurrently with or after the 16th rising clock edge, but remains unaltered. Shutdown can be used to save power before the next rising clock edge or data will be lost. or as an alarm to flash the display by successively entering Data at DIN is propagated through the shift register and and leaving shutdown mode. For minimum supply current appears at DOUT 16.5 clock cycles later. Data is clocked in shutdown mode, logic inputs should be at ground or V+ out on the falling edge of CLK. Data bits are labeled (CMOS-logic levels). D0–D15 (Table 1). D8–D11 contain the register address. D0–D7 contain the data, and D12–D15 are “don’t care” Typically, it takes less than 250μs for the MAX7219/ bits. The first received is D15, the most significant bit MAX7221 to leave shutdown mode. The display driver can (MSB). be programmed while in shutdown mode, and shutdown mode can be overridden by the display-test function. www.maximintegrated.com Maxim Integrated │ 6