Datasheet MAX7219, MAX7221 (Analog Devices) - 3
| 制造商 | Analog Devices |
| 描述 | Serially Interfaced, 8-Digit, LED Display Drivers |
| 页数 / 页 | 15 / 3 — Electrical Characteristics (continued). PARAMETER. SYMBOL. CONDITIONS. … |
| 文件格式/大小 | PDF / 1.4 Mb |
| 文件语言 | 英语 |
Electrical Characteristics (continued). PARAMETER. SYMBOL. CONDITIONS. MIN. TYP. MAX. UNITS. LOGIC INPUTS. TIMING CHARACTERISTICS
该数据表的模型线
文件文字版本
MAX7219/MAX7221 Serially Interfaced, 8-Digit LED Display Drivers
Electrical Characteristics (continued)
(V+ = 5V ±10%, RSET = 9.53kΩ ±1%, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS LOGIC INPUTS
Input Current DIN, CLK, LOAD, CS IIH, IIL VIN = 0V or V+ -1 1 µA Logic High Input Voltage VIH 3.5 V Logic Low Input Voltage VIL 0.8 V Output High Voltage VOH DOUT, ISOURCE = -1mA V+ - 1 V Output Low Voltage VOL DOUT, ISINK = 1.6mA 0.4 V Hysteresis Voltage ΔVI DIN, CLK, LOAD, CS 1 V
TIMING CHARACTERISTICS
CLK Clock Period tCP 100 ns CLK Pulse Width High tCH 50 ns CLK Pulse Width Low tCL 50 ns CS Fall to SCLK Rise Setup Time (MAX7221 only) tCSS 25 ns CLK Rise to CS or LOAD Rise Hold Time tCSH 0 ns DIN Setup Time tDS 25 ns DIN Hold Time tDH 0 ns Output Data Propagation Delay tDO CLOAD = 50pF 25 ns Load-Rising Edge to Next Clock Rising Edge (MAX7219 only) tLDCK 50 ns Minimum CS or LOAD Pulse High tCSW 50 ns Data-to-Segment Delay tDSPD 2.25 ms www.maximintegrated.com Maxim Integrated │ 3
Electrical Characteristics (continued)
(V+ = 5V ±10%, RSET = 9.53kΩ ±1%, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS LOGIC INPUTS
Input Current DIN, CLK, LOAD, CS IIH, IIL VIN = 0V or V+ -1 1 µA Logic High Input Voltage VIH 3.5 V Logic Low Input Voltage VIL 0.8 V Output High Voltage VOH DOUT, ISOURCE = -1mA V+ - 1 V Output Low Voltage VOL DOUT, ISINK = 1.6mA 0.4 V Hysteresis Voltage ΔVI DIN, CLK, LOAD, CS 1 V
TIMING CHARACTERISTICS
CLK Clock Period tCP 100 ns CLK Pulse Width High tCH 50 ns CLK Pulse Width Low tCL 50 ns CS Fall to SCLK Rise Setup Time (MAX7221 only) tCSS 25 ns CLK Rise to CS or LOAD Rise Hold Time tCSH 0 ns DIN Setup Time tDS 25 ns DIN Hold Time tDH 0 ns Output Data Propagation Delay tDO CLOAD = 50pF 25 ns Load-Rising Edge to Next Clock Rising Edge (MAX7219 only) tLDCK 50 ns Minimum CS or LOAD Pulse High tCSW 50 ns Data-to-Segment Delay tDSPD 2.25 ms www.maximintegrated.com Maxim Integrated │ 3