Datasheet TEA5767HN (NXP) - 10

NXP Semiconductors TEA5767HN Low-power FM stereo radio for handheld applications 8. I2C-bus, 3-wire bus and bus-controlled functions 8.1 I2C-bus specification
Information about the I2C-bus can be found in the brochure “The I2C-bus and how to use it” (order number 9398 393 40011). The standard I2C-bus specification is expanded by the following definitions: IC address: 110 0000b Structure of the I2C-bus logic: slave transceiver Subaddresses are not used The maximum LOW-level input and the minimum HIGH-level input are specified to 0.2VCCD and 0.45VCCD respectively. The pin BUSMODE must be connected to ground to operate the IC with the I2C-bus.
Remark:
The I2C-bus operates at a maximum clock frequency of 400 kHz. It is not allowed to connect the IC to an I2C-bus operating at a higher clock rate.
8.1.1 Data transfer
Data sequence: address, byte 1, byte 2, byte 3, byte 4 and byte 5 (the data transfer has to be in this order). The Least Significant Bit (LSB) = 0 of the address indicates a WRITE operation to the TEA5767HN. Bit 7 of each byte is considered as the Most Significant Bit (MSB) and has to be transferred as the first bit of the byte. The data becomes valid bitwise at the appropriate falling edge of the clock. A STOP condition after any byte can shorten transmission times. When writing to the transceiver by using the STOP condition before completion of the whole transfer:
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The remaining bytes will contain the old information
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If the transfer of a byte is not completed, the new bits will be used, but a new tuning cycle will not be started The IC can be switched into a low current Standby mode with the standby bit; the bus is then still active. The standby current can be reduced by deactivating the bus interface (pin BUSENABLE LOW). If the bus interface is deactivated (pin BUSENABLE LOW) without the Standby mode being programmed, the IC maintains normal operation, but is isolated from the bus lines. The software programmable output (SWPORT1) can be programmed to operate as a tuning indicator output. As long as the IC has not completed a tuning action, pin SWPORT1 remains LOW. The pin becomes HIGH, when a preset or search tuning is completed or when a band limit is reached. The reference frequency divider of the synthesizer PLL is changed when the MSB in byte 5 is set to logic 1. The tuning system can then be clocked via pin XTAL2 at 6.5 MHz. TEA5767HN_5 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 05 — 26 January 2007 10 of 40
Document Outline 1. General description 2. Features 3. Quick reference data 4. Ordering information 5. Block diagram 6. Pinning information 6.1 Pinning 6.2 Pin description 7. Functional description 7.1 Low-noise RF amplifier 7.2 FM mixer 7.3 VCO 7.4 Crystal oscillator 7.5 PLL tuning system 7.6 RF AGC 7.7 IF filter 7.8 FM demodulator 7.9 Level voltage generator and analog-to-digital converter 7.10 IF counter 7.11 Soft mute 7.12 MPX decoder 7.13 Signal dependent mono to stereo blend 7.14 Signal dependent AF response 7.15 Software programmable ports 7.16 I2C-bus and 3-wire bus 8. I2C-bus, 3-wire bus and bus-controlled functions 8.1 I2C-bus specification 8.1.1 Data transfer 8.1.2 Power-on reset 8.2 I2C-bus protocol 8.3 3-wire bus specification 8.3.1 Data transfer 8.3.2 Power-on reset 8.4 Writing data 8.5 Reading data 9. Internal circuitry 10. Limiting values 11. Thermal characteristics 12. Static characteristics 13. Dynamic characteristics 14. FM characteristics 15. I2C-bus characteristics 16. Test information 17. Package outline 18. Soldering 18.1 Introduction to soldering 18.2 Wave and reflow soldering 18.3 Wave soldering 18.4 Reflow soldering 19. Revision history 20. Legal information 20.1 Data sheet status 20.2 Definitions 20.3 Disclaimers 20.4 Trademarks 21. Contact information 22. Contents