Datasheet LAN8022 (Microchip)

LAN8022 Dual 1G/10G/25G MACsec Optical Ethernet PHY Transceiver Highlights
• Two 1G/10G/25G serial Host interfaces • PCS Retimer mode - IEEE 802.3-2018 compliant - Ful y configurable Ethernet PHY on Host and Line - Backplane Ethernet with KR/RS FEC - Host and Line must be of same speed but can be • Two 1G/10G/25G serial Line interfaces of dif erent formats (e.g. Host is Backplane Ethernet with KR FEC, - IEEE 802.3-2018 compliant Line is Optical Ethernet with RS FEC) - SFP, XFP, SFP+, QSFP+, SFP28 & QSFP28 - Host and Line may be synchronous or may have • Integrated cross-connect features PPM clock dif erences handled by rate adaptation - Any line port connectible to any host port - TSN Frame Preemption support - 1:1 and 1+1 host redundancy • MAC Retimer (Ethernet serial PHY with MACsec • IEEE 802.1AE-2018 MACsec mode) • Unencrypted VLAN tags per - Ful y configurable Ethernet MAC and PHY on Host IEEE 802.1AE-2018 (was 802.1AEcg) and Line • Encrypted Ethernet inside unencrypted MPLS - Host and Line must be of the same speed (e.g., headers 25G Ethernet), but can be of dif erent formats (e.g., KR FEC on Host and FEC on Line) • TSN frame preemption - Host and Line may be ful y synchronous or may • PCS and MAC retimer modes have PPM clock dif erences handled by rate adap- • 256-BALL HFC-BGA (14 x 14 mm) tation • Extended temperature range - TSN Frame Preemption support -40°C (T - MACsec support A) to +110°C (TJ) • IEEE 802.3-2018 support for:
Target Applications
- 1000BASE: KX, SX, LX - 10GBASE: “CR”, KR, SR, LR, ER • 5G Smal Cel -KR: KR FEC, ANEG, Training • Industrial - 25GBASE: CR, CR-S, KR, KR-S, SR, LR, ER • Enterprise IT -KR FEC, RSE FEC,ANEG, Training • Broadband • Loopback support • Diagnostics
Key Benefits
- RX Eye Monitor plot - PRBS generator/checker • MACsec support • Support for jumbo frames up to 10 KB (10,240 - Compliant to IEEE 802.1AE-2018, providing Confi- bytes) dentiality, Anti-Replay Protection and Data Integrity • PHY Management Interface is MDIO or SPI - GCM-AES-128 and GCM-AES-256 configurable per-SA - High-speed SPI can be used simultaneously with MDIO to support high-bandwidth - Port-based and Flow-based encryption with 128 management needs of MACsec SAKs supporting up to 64 SAs per port, with statistics kept per SA, vPort, and Port • Pin-strapping options - VLAN Tag Bypass (tag in clear) of up to four VLAN • 40 GPIOs which alternately support: tags - Two-wire Module Management Interface per port - Extended Packet Numbering (XPN) - Two chip Interrupts - TSN Support: - Two LEDs (Link, Activity) per port -Frame Preemption • Coma mode support to eliminate port link bounc- -MACsec bandwidth expansion handled using ing at startup and to synchronize LEDs TSN-friendly constant rate formats (Pause flow control also supported) • Power down and power saving modes - MACsec EtherType is configurable per-port • Reference clock inputs - MACsec of Ethernet over MPLS (EoMPLS) with up - System Reference Clock to five MPLS labels (MPLS header unencrypted)  2025 Microchip Technology Inc. and its subsidiaries DS00006160B-page 1 Document Outline Table of contents 1.0 Introduction 1.1 General Description 2.0 Pin Descriptions 2.1 Pin Assignments 2.2 Pin Descriptions 2.3 Buffer Types 3.0 Functional Descriptions 3.1 IEEE 802.3 Alignment 3.2 Data Path Overview 3.2.1 Operating Modes 3.2.2 MACsec 3.2.3 SerDEs 3.2.4 PCS25G 3.2.5 1G PCS 3.2.6 Cross Connect 3.2.7 MAC 3.2.8 Flow Control Buffer 3.2.9 MACsec 3.2.10 Loopbacks and Packet BIST 3.3 Frame Preemption Verify/Respond System Operation 3.4 Link Fault Signaling System Operation 3.5 Flow Control System Operation 3.5.1 Pause Handling and Flow Control 3.5.2 Basic Flow Control Handling 3.5.3 Advanced Flow Control Handling 3.6 Auto-negotiation and Training 3.6.1 25G Technology Ability 3.7 MACsec Operation 3.7.1 MACsec Crypto 3.7.2 MACsec Capture FIFO 3.7.3 Debug Fault Code in CRC 3.7.4 MACsec Frame Encapsulations and Transforms 3.7.5 MACsec Host Formats 3.8 Clocking 3.8.1 Data Path Clocking 3.8.2 System Clock Generation 3.8.3 Synchronous Ethernet and Recovered Clocks 3.9 Device Management 3.9.1 SPI Client Interface 3.9.2 Management Data Input/Output (MDIO) Interface 3.10 Fiber Modules and Management 3.10.1 Two-Wire Interface 3.10.2 Fiber Module Support 3.11 LEDs 3.12 GPIOs 3.12.1 GPIO Interrupts 3.13 Resets and Power-On Self-Test 3.13.1 Resets 3.14 Host Interrupts 3.15 JTAG 3.15.1 Test TAP Controller 3.15.2 Test Modes 3.15.3 CSR Ring Access 3.15.4 Boundary Scan 3.16 Miscellaneous 3.16.1 Power Management 3.16.2 Warm ReSTART 3.16.3 Temperature Sensor 3.17 Configuration Straps 3.17.1 Function Mode Straps 4.0 Operational Characteristics 4.1 Absolute Maximum Ratings* 4.2 Operating Conditions** 4.3 Package Thermal Specifications 4.3.1 256-BGA 4.4 Power Consumption 4.4.1 Worst Case TWO Port Operation 4.4.2 Typical Usage TWO Port Operation 4.5 DC Specifications 4.5.1 SYSREFCK And LREFCK Clock Inputs DC Electrical Characteristics 4.5.2 SerDes DC Electrical Characteristics 4.6 AC Specifications 4.6.1 Power Sequencing 4.6.2 SYSREFCK And LREFCK Clock Inputs AC Electrical Characteristics 4.6.3 SerDes AC Electrical Characteristics 4.6.4 TWI Host Timing 4.6.5 MDC/MDIO Client 4.6.6 SPI Client 4.6.7 Recovered Clock Timing Requirements 4.6.8 Reset Pin Configuration Strap Timing 4.6.9 JTAG Timing Values 5.0 Package Information 5.1 Top Marking 5.2 256-BGA Appendix A: Data Sheet Revision History Product Identification System The Microchip Web Site Customer Change Notification Service Customer Support