Datasheet SN74LVC1G74 (Texas Instruments) - 10
| 制造商 | Texas Instruments |
| 描述 | Single Positive-Edge-Triggered D-Type Flip-Flop With Clear and Preset |
| 页数 / 页 | 31 / 10 — SN74LVC1G74. www.ti.com. 8 Detailed Description 8.1 Overview. 8.2 … |
| 文件格式/大小 | PDF / 1.4 Mb |
| 文件语言 | 英语 |
SN74LVC1G74. www.ti.com. 8 Detailed Description 8.1 Overview. 8.2 Functional Block Diagram. PRE. CLK. CLR. 8.3 Feature Description
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SN74LVC1G74
SCES794G – OCTOBER 2009 – REVISED SEPTEMBER 2021
www.ti.com 8 Detailed Description 8.1 Overview
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
8.2 Functional Block Diagram 7 PRE 1 C CLK C C 5 Q TG C C C C 2 D TG TG TG 3 Q C C C 6 CLR 8.3 Feature Description
• Allow down voltage translation – 5-V to 3.3-V – 5.0-V to 1.8-V – 3.3-V to 1.8-V • Inputs accept voltage levels up to 5.5-V • Ioff Feature – Can prevent backflow current that can damage device when powered down
8.4 Device Functional Modes Table 8-1. Function Table INPUTS OUTPUTS PRE CLR CLK D Q Q
L H X X H L H L X X L H L L X X H(1) H(1) H H ↑ H H L H H ↑ L L H H H L X Q0 Q 0 (1) This configuration is nonstable; that is, it does not persist when PRE or CLR returns to its inactive (high) level. 10 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN74LVC1G74 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Revision History 5 Pin Configuration and Functions 6 Specifications 6.1 Absolute Maximum Ratings 6.2 ESD Ratings 6.3 Recommended Operating Conditions 6.4 Thermal Information 6.5 Electrical Characteristics 6.6 Timing Requirements 6.7 Switching Characteristics 6.8 Operating Characteristics 6.9 Typical Characteristics 7 Parameter Measurement Information 8 Detailed Description 8.1 Overview 8.2 Functional Block Diagram 8.3 Feature Description 8.4 Device Functional Modes 9 Application and Implementation 9.1 Application Information 9.2 Typical Power Button Circuit 9.2.1 Design Requirements 9.2.2 Detailed Design Procedure 9.2.3 Application Curves 10 Power Supply Recommendations 11 Layout 11.1 Layout Guidelines 11.2 Layout Example 12 Device and Documentation Support 12.1 Receiving Notification of Documentation Updates 12.2 Support Resources 12.3 Trademarks 12.4 Electrostatic Discharge Caution 12.5 Glossary 13 Mechanical, Packaging, and Orderable Information
SN74LVC1G74
SCES794G – OCTOBER 2009 – REVISED SEPTEMBER 2021
www.ti.com 8 Detailed Description 8.1 Overview
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
8.2 Functional Block Diagram 7 PRE 1 C CLK C C 5 Q TG C C C C 2 D TG TG TG 3 Q C C C 6 CLR 8.3 Feature Description
• Allow down voltage translation – 5-V to 3.3-V – 5.0-V to 1.8-V – 3.3-V to 1.8-V • Inputs accept voltage levels up to 5.5-V • Ioff Feature – Can prevent backflow current that can damage device when powered down
8.4 Device Functional Modes Table 8-1. Function Table INPUTS OUTPUTS PRE CLR CLK D Q Q
L H X X H L H L X X L H L L X X H(1) H(1) H H ↑ H H L H H ↑ L L H H H L X Q0 Q 0 (1) This configuration is nonstable; that is, it does not persist when PRE or CLR returns to its inactive (high) level. 10 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN74LVC1G74 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Revision History 5 Pin Configuration and Functions 6 Specifications 6.1 Absolute Maximum Ratings 6.2 ESD Ratings 6.3 Recommended Operating Conditions 6.4 Thermal Information 6.5 Electrical Characteristics 6.6 Timing Requirements 6.7 Switching Characteristics 6.8 Operating Characteristics 6.9 Typical Characteristics 7 Parameter Measurement Information 8 Detailed Description 8.1 Overview 8.2 Functional Block Diagram 8.3 Feature Description 8.4 Device Functional Modes 9 Application and Implementation 9.1 Application Information 9.2 Typical Power Button Circuit 9.2.1 Design Requirements 9.2.2 Detailed Design Procedure 9.2.3 Application Curves 10 Power Supply Recommendations 11 Layout 11.1 Layout Guidelines 11.2 Layout Example 12 Device and Documentation Support 12.1 Receiving Notification of Documentation Updates 12.2 Support Resources 12.3 Trademarks 12.4 Electrostatic Discharge Caution 12.5 Glossary 13 Mechanical, Packaging, and Orderable Information