Register Description R820T2 (Rafael Micro) - 5
| 制造商 | Rafael Micro |
| 描述 | High Performance Low Power Advanced Digital TV Silicon Tuner in QFN-24 package |
| 页数 / 页 | 11 / 5 — 1.2 Control Registers. Register Configuration |
| 文件格式/大小 | PDF / 229 Kb |
| 文件语言 | 英语 |
1.2 Control Registers. Register Configuration

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1.2 Control Registers Register Configuration
Total 32 registers are programmable to set the major functions of R820T2. The register matrix in table 1-2 outlines the structure of register bit. Detail register description is listed in the next section: Table 1-2 : Register Matrix Reg Reg Write B7 B6 B5 B4 B3 B2 B1 B0 Address Name /Read 0x00 R0 R 1 0 0 1 0 1 1 0 0x01 R1 R - - - - - - - - 0x02 R2 R 0 VCO_INDICATOR[6:0] 0x03 R3 R RF_INDICATOR [7:0] 0x04 R4 R - - - - - - - - 0x05 R5 W/R PWD_LT 0 PWD_LNA1 LNA_GAIN_MODE LNA_GAIN[3:0] 0x06 R6 W/R PWD_PDET1 PWD_PDET3 FILT_3DB 1 0 PW_LNA[2:0] 0x07 R7 W/R 0 PWD_MIX PW0_MIX MIXGAIN_MODE MIX_GAIN[3:0] 0x08 R8 W/R PWD_AMP PW0_AMP IMR_G[5:0] 0x09 R9 W/R PWD_IFFILT PW1_IFFILT IMR_P[5:0] 0x0A R10 W/R PWD_FILT PW_FILT 1 FILT_CODE[3:0] 0x0B R11 W/R 0 FILT_BW[1:0] 0 HPF[3:0] 0x0C R12 W/R 1 PWD_VGA 1 VGA_MODE VGA_CODE[3:0] 0x0D R13 W/R LANVTH_H[3:0] LNAVTH_L[3:0] 0x0E R14 W/R MIXVTH_H[3:0] MIXVTH_L[3:0] 0x0F R15 W/R 0 0 1 CLK_OUT_ENB 1 0 CLK_AGC_ENB 0 0x10 R16 W/R SEL_DIV[2:0] REF_DIV2 0 1 CAPX[1:0] 0x11 R17 W/R PW_LDO_A[1:0] 0 0 0 0 1 1 0x12 R18 W/R 1 0 0 0 PW_SDM 0 0 0 0x13 R19 W/R 0 0 0 0 0 0 0 0 0x14 R20 W/R S_I2C[1:0] N_I2C[4:0] 0x15 R21 W/R SDM_IN[8:1] 0x16 R22 W/R SDM_IN[16:9] 0x17 R23 W/R PW_LDO_D[1:0] 1 1 OPEN_D 1 0 0 0x18 R24 W/R 0 1 - - - - - - 0x19 R25 W/R PWD_RFFILT 0 0 SW_AGC 1 1 - - 0x1A R26 W/R RFMUX[1:0] 1 0 PLL_AUTO_CLK[1:0] RFFILT{1:0] 0x1B R27 W/R TF_NCH[3:0] TF_LP[3:0] 0x1C R28 W/R PDET3_GAIN[3:0] 0 1 - 0 0x1D R29 W/R 1 1 PDET1_GAIN[2:0] PDET2_GAIN[2:0] 0x1E R30 W/R 0 1 PDET_CLK[4:0] 0x1F R31 W/R 1 1 0 0 0 0 - - CONFIDENTIAL © 2012 by Rafael Microelectronics, Inc. All rights reserved. 5