Datasheet SI7489DP (Vishay) - 8

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Power MOSFETs
Application Note AN821
PowerPAK
®
SO-8 Mounting and Thermal Considerations by Wharton McDaniel PowerPAK SO-8 SINGLE MOUNTING
MOSFETs for switching applications are now available with The PowerPAK single is simple to use. The pin arrangement die on resistances around 1 m and with the capability to (drain, source, gate pins) and the pin dimensions are the handle 85 A. While these die capabilities represent a major same as standard SO-8 devices (see figure 2). Therefore, the advance over what was available just a few years ago, it is PowerPAK connection pads match directly to those of the important for power MOSFET packaging technology to keep SO-8. The only difference is the extended drain connection pace. It should be obvious that degradation of a high area. To take immediate advantage of the PowerPAK SO-8 performance die by the package is undesirable. PowerPAK single devices, they can be mounted to existing SO-8 land is a new package technology that addresses these issues. patterns. In this application note, PowerPAK’s construction is described. Following this mounting information is presented including land patterns and soldering profiles for maximum reliability. Finally, thermal and electrical performance is discussed.
THE PowerPAK PACKAGE
The PowerPAK package was developed around the SO-8 package (figure 1). The PowerPAK SO-8 utilizes the same footprint and the same pin-outs as the standard SO-8. This Standard SO-8 PowerPAK SO-8 allows PowerPAK to be substituted directly for a standard SO-8 package. Being a leadless package, PowerPAK SO-8 Fig. 2 utilizes the entire SO-8 footprint, freeing space normally occupied by the leads, and thus allowing it to hold a larger die than a standard SO-8. In fact, this larger die is slightly The minimum land pattern recommended to take full larger than a full sized DPAK die. The bottom of the die advantage of the PowerPAK thermal performance see attach pad is exposed for the purpose of providing a direct, Application Note 826, Recommended Minimum Pad low resistance thermal path to the substrate the device is Patterns With Outline Drawing Access for Vishay Siliconix mounted on. Finally, the package height is lower than the MOSFETs. Click on the PowerPAK SO-8 single in the index standard SO-8, making it an excellent choice for of this document. applications with space constraints. In this figure, the drain land pattern is given to make full contact to the drain pad on the PowerPAK package. This land pattern can be extended to the left, right, and top of the drawn pattern. This extension will serve to increase the heat dissipation by decreasing the thermal resistance APPLIC from the foot of the PowerPAK to the PC board and therefore to the ambient. Note that increasing the drain land area beyond a certain point will yield little decrease in foot-to-board and foot-to-ambient thermal resistance. Under specific conditions of board configuration, copper ATION N weight and layer stack, experiments have found that more than about 0.25 in2 to 0.5 in2 of additional copper (in addition to the drain land) will yield little improvement in thermal performance. O Fig. 1 PowerPAK 1212 Devices TE Revision: 16-Mai-13
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