Datasheet Si5351 (Silicon Labs)

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S i 5 3 5 1 A / B / C - B I 2C - P ROGRAMMABLE A NY- F REQUENCY C M O S C LOCK G ENERATOR + V C X O Features
www.silabs.com/custom-timing Glitchless frequency changes
10-MSOP
Generates up to 8 non-integer-related Separate voltage supply pins provide frequencies from 2.5 kHz to 200 MHz level translation: I2C user definable configuration Core VDD: 2.5 or 3.3 V Exact frequency synthesis at each output Output VDDO: 1.8, 2.5, or 3.3 V (0 ppm error) Excellent PSRR eliminates external Highly linear VCXO power supply filtering Optional clock input (CLKIN) Very low power consumption
20-QFN
Low output period jitter: < 70 ps pp, typ Adjustable output delay Configurable spread spectrum selectable Available in 2 packages types: at each output 10-MSOP: 3 outputs Operates from a low-cost, fixed frequency 20-QFN (4x4 mm): 8 outputs crystal: 25 or 27 MHz PCIE Gen 1 compatible Supports static phase offset Supports HCSL compatible swing Programmable rise/fall time control
Ordering Information:
See page 29
Applications
HDTV, DVD/Blu-ray, set-top box Residential gateways Audio/video equipment, gaming Networking/communication Printers, scanners, projectors Servers, storage Handheld Instrumentation XO replacement
Description
The Si5351 is an I2C configurable clock generator that is ideally suited for replacing crystals, crystal oscillators, VCXOs, phase-locked loops (PLLs), and fanout buffers in cost-sensitive applications. Based on a PLL/VCXO + high resolution MultiSynth fractional divider architecture, the Si5351 can generate any frequency up to 200 MHz on each of its outputs with 0 ppm error. Three versions of the Si5351 are available to meet a wide variety of applications. The Si5351A generates up to 8 free-running clocks using an internal oscillator for replacing crystals and crystal oscillators. The Si5351B adds an internal VCXO and provides the flexibility to replace both free-running clocks and synchronous clocks. It eliminates the need for higher cost, custom pullable crystals while providing reliable operation over a wide tuning range. The Si5351C offers the same flexibility but synchronizes to an external reference clock (CLKIN).
Functional Block Diagram Si5351C (20-QFN) Si5351B (20-QFN)
VDDOA VDDOA MultiSynth MultiSynth R0 R0 XA XA 0 CLK0 0 CLK0 PLL PLL OSC OSC MultiSynth A CLK1 MultiSynth CLK1 R1 XB XB R1 1 1 VDDOB VDDOB MultiSynth VCXO MultiSynth PLL R2 R2 2 CLK2 2 CLK2 CLKIN B VC MultiSynth CLK3 MultiSynth CLK3 R3 R3 3 3 VDDOC VDDOC MultiSynth MultiSynth R4 SDA R4 4 CLK4 SDA 4 CLK4 I2C SCL I2C MultiSynth CLK5 MultiSynth CLK5 R5 SCL R5 5 5 INTR VDDOD VDDOD MultiSynth MultiSynth R6 OEB R6 6 CLK6 Control 6 CLK6 Control OEB Logic MultiSynth CLK7 SSEN MultiSynth CLK7 Logic R7 R7 7 7
Rev. 1.0 4/15 Copyright © 2015 by Silicon Laboratories Si5351A/B/C-B
Document Outline 1. Electrical Specifications 2. Detailed Block Diagrams 3. Functional Description 3.1. Input Stage 3.1.1. Crystal Inputs (XA, XB) 3.1.2. External Clock Input (CLKIN) 3.1.3. Voltage Control Input (VC) 3.2. Synthesis Stages 3.3. Output Stage 3.4. Spread Spectrum 3.5. Control Pins (OEB, SSEN) 3.5.1. Output Enable (OEB) 3.5.2. Spread Spectrum Enable (SSEN)—Si5351A and Si5351B only 4. I2C Interface 5. Configuring the Si5351 5.1. Writing a Custom Configuration to RAM 5.2. Si5351 Application Examples 5.3. Replacing Crystals and Crystal Oscillators 5.4. Replacing Crystals, Crystal Oscillators, and VCXOs 5.5. Replacing Crystals, Crystal Oscillators, and PLLs 5.6. Applying a Reference Clock at XTAL Input 5.7. HCSL Compatible Outputs 6. Design Considerations 6.1. Power Supply Decoupling/Filtering 6.2. Power Supply Sequencing 6.3. External Crystal 6.4. External Crystal Load Capacitors 6.5. Unused Pins 6.6. Trace Characteristics 7. Register Map Summary 8. Register Descriptions 9. Si5351 Pin Descriptions 9.1. Si5351A 20-pin QFN 9.2. Si5351B 20-Pin QFN 9.3. Si5351C 20-Pin QFN 9.4. Si5351A 10-Pin MSOP 10. Ordering Information 11. Package Outlines 11.1. 20-pin QFN 12. Land Pattern: 20-Pin QFN 12.1. 10-Pin MSOP Package Outline 13. Land Pattern: 10-Pin MSOP 14. Top Marking 14.1. 20-Pin QFN Top Marking 14.2. Top Marking Explanation 14.3. 10-Pin MSOP Top Marking 14.4. Top Marking Explanation Document Change List